Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.

Abstract: Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.

Abstract: A communication cable includes a cable core including a plurality of pairs of wires, each of the pairs of wires being formed by spirally twisting two wires including conductors covered with an insulator, and an external jacket configured to cover an outer side of the cable core, where the external jacket includes a plurality of support arms to prevent contact between the cable core and an inner surface of the external jacket and to secure a separation space in a radial direction, the plurality of support arms being integrally formed with the external jacket, and each of the plurality of support arms including a connection part connected to the inner surface of the external jacket and a support part having an increased width at an end portion of the connection part to support the cable core, thereby enabling the communication cable to satisfy a standard of Cat.6A or higher.

Abstract: A makeup evaluation system according to an embodiment of the present invention includes a mobile terminal for photographing a facial image and transmitting the photographed facial image to a makeup server, and the makeup server for storing makeup score data and, when receiving the facial image from the mobile terminal, detecting at least one face region in the facial image, calculating a makeup score for each of the detected face regions on the basis of the makeup score data, and transmitting the calculated makeup score to the mobile terminal.

Abstract: The present invention relates to a communication cable capable of satisfying the communication cable standard of Cat. 6A or higher by minimizing interference between adjacent cables by a method of changing a structure of an external jacket without applying a metal shielding layer to cover each pair of wires or a whole cable core.

Abstract: A fan-out semiconductor package includes: a support member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The support member includes a glass plate and an insulating layer connected to the glass plate.

Abstract: A fan-out semiconductor package includes: a support member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The support member includes a glass plate and an insulating layer connected to the glass plate.

Abstract: A one time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells provided at locations where a plurality of word lines and a plurality of bit lines cross each other, and a write circuit configured to sequentially program the OTP cells by selecting the bit lines one at a time and program a selected OTP cell connected to the selected bit line, wherein the write circuit is further configured to detect a voltage level of the selected bit line and select another bit line when the detected voltage level indicates that the selected OTP cell is in a programmed state.

Abstract: A fuse memory comprising a discharge circuit is provided. The fuse memory includes a fuse cell array comprising fuse cells connected to read word lines, programs word lines, and bit lines arranged in rows and columns; and at least one discharge circuit arranged in each of the rows. The discharge circuit discharges a voltage level of a program word line of the fuse cells selected in a read mode to a ground voltage.

Abstract: A one time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells provided at locations where a plurality of word lines and a plurality of bit lines cross each other, and a write circuit configured to sequentially program the OTP cells by selecting the bit lines one at a time and program a selected OTP cell connected to the selected bit line, wherein the write circuit is further configured to detect a voltage level of the selected bit line and select another bit line when the detected voltage level indicates that the selected OTP cell is in a programmed state.

Abstract: A fuse memory comprising a discharge circuit is provided. The fuse memory includes a fuse cell array comprising fuse cells connected to read word lines, programs word lines, and bit lines arranged in rows and columns; and at least one discharge circuit arranged in each of the rows. The discharge circuit discharges a voltage level of a program word line of the fuse cells selected in a read mode to a ground voltage.

Abstract: In a one-time programmable (OTP) memory and a method of testing the same. The OTP memory includes an OTP cell array comprising OTP cells which are activated by an address received from a source external to the OTP memory and which OTP cells are unprogrammed. A test cell array includes a first test row having unprogrammed first test cells and a second test row having mask-programmed second test cells, and sharing bit lines extending in a column direction with the OTP cell array. The first test cells and second test cells are accessible during testing of the OTP cell array.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device comprising a substrate including a first surface and a second surface that face each other, a planarization layer formed on the first surface of the substrate, a passivation layer formed on the planarization layer, and a through via contact penetrating the substrate, the planarization layer, and the passivation layer, and being exposed from the passivation layer.

Abstract: An apparatus and method for human activity and facial expression modeling and recognition are based on feature extraction techniques from time sequential images. The human activity modeling includes determining principal components of depth and/or binary shape images of human activities extracted from video clips. Independent Component Analysis (ICA) representations are determined based on the principal components. Features are determined through Linear Discriminant Analysis (LDA) based on the ICA representations. A codebook is determined using vector quantization, Observation symbol sequences in the video clips am determined. And human activities are learned using the Hidden Markov Model (HMM) based on status transition and an observation matrix.

Abstract: Provided are a semiconductor device and a semiconductor package. The semiconductor device includes semiconductor device includes a semiconductor substrate having a first side and a second side. A front-side structure including an internal circuit is disposed on the first side of the semiconductor substrate. A passivation layer is disposed on the second side of the semiconductor substrate. A through-via structure passes through the semiconductor substrate and the passivation layer. A back-side conductive pattern is disposed on the second side of the semiconductor substrate. The back-side conductive pattern is electrically connected to the through-via structure. An alignment recessed area is disposed in the passivation layer. An insulating alignment pattern is disposed in the alignment recessed area.

Abstract: A printed circuit board, a semiconductor package and a method of manufacturing the same are provided. The printed circuit board includes an insulation layer, an electronic component embedded within the insulation layer, a component guide affixing the embedded electronic component at an installed position, and a circuit layer disposed in the insulation layer.

Abstract: An electronic component embedded printed circuit board and method thereof a first insulation layer, an electronic component, a second insulation layer, and a circuit layer. The first insulation layer includes a trench formed therein. The electronic component is installed in the trench. The second insulation layer is formed above the first insulation layer and the electronic component. The circuit layer is formed on the first insulation layer and on the second insulation layer.

Abstract: An electronic device embedded substrate and a method of manufacturing the same are disclosed. The electronic device embedded substrate in accordance with an aspect of the present invention includes: an electronic device; and a core substrate having a cavity, in which the electronic device is embedded and of which a width of at least a portion is smaller than widths of other portions thereof.

Abstract: Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad.

Abstract: Provided are a semiconductor device and a semiconductor package. The semiconductor device includes semiconductor device includes a semiconductor substrate having a first side and a second side. A front-side structure including an internal circuit is disposed on the first side of the semiconductor substrate. A passivation layer is disposed on the second side of the semiconductor substrate. A through-via structure passes through the semiconductor substrate and the passivation layer. A back-side conductive pattern is disposed on the second side of the semiconductor substrate. The back-side conductive pattern is electrically connected to the through-via structure. An alignment recessed area is disposed in the passivation layer. An insulating alignment pattern is disposed in the alignment recessed area.