Abstract: A memory device may include a plurality of first sense amplifiers including a plurality of corresponding first input terminals, a plurality of second sense amplifiers including a plurality of corresponding second input terminals, the plurality of first and second sense amplifiers being suitable for amplifying data received through the respective plurality of first and second input terminals, and for outputting the amplified data which include first and second data outputted by the plurality of first sense amplifiers and third and fourth data outputted by the plurality of second sense amplifiers; a plurality of first pipe latches suitable for latching and outputting the first and second data at a specific interval; a plurality of second pipe latches suitable for latching and outputting the third and fourth data at a specific interval; and an input/output line coupled to the plurality of first and second pipe latches, suitable for outputting the first, second, third and fourth data.

Abstract: A semiconductor device may include: a plurality of output paths, which include a plurality of through silicon vias (TSVs), respectively, and suitable for transmission of test confirmation information; an information provider suitable for providing the test confirmation information to the plurality of TSVs; and an output controller suitable for selectively blocking one of the output paths including a failed one among the plurality of TSVs.

Abstract: An operation method of a memory device may include writing first data to a plurality of memory cells corresponding to a plurality of word lines, enabling a sense amplifier corresponding to the memory cells and setting second data in the sense amplifier, the second data having the opposite phase of the first data, and sequentially enabling the plurality of word lines for a predetermined time while enabling the sense amplifier.

Abstract: A self-refresh control device may be provided. The self-refresh control device may include a refresh signal output circuit configured to generate self-refresh signals with an oscillator and provide a refresh signal. The self-refresh control device may begin a self-refresh mode in response to a clock enable signal and a self-refresh signal within a self-refresh entry period, and may prevent performance of a new self-refresh operation by delaying an additional self-refresh signal until after the self-refresh entry period has ended.

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract: A mobile image forming apparatus and an image compensation method of the mobile image forming apparatus are provided. The mobile image forming apparatus includes a surface measurer configured to measure an area touched by the mobile image forming apparatus among a surface area on which a print image is to be printed, an image processor configured to retrieve at least one of curvature data and moisture data from the measured result, and compensate the print image based on the at least one of the curvature data and moisture data retrieved, and an image former configured to print the compensated print image on the surface.

Abstract: A repair circuit includes a normal decoder suitable for decoding partial input addresses of input addresses in response to a first control signal, a comparison unit suitable for comparing the partial input addresses and partial repair addresses of repair addresses in response to a second control signal, and generating a column repair signal when the partial input addresses and the partial repair addresses correspond to each other, and a redundancy decoder suitable for decoding the repair addresses in response to the column repair signal.

Abstract: A circuit of a semiconductor memory device may include a delay unit suitable for delaying a column pulse signal, and sequentially generating a first strobe source signal, a column source signal, and a second strobe source signal at a predetermined time interval, and an input/output strobe signal generation unit suitable for generating an input/output strobe signal which is activated during a period in which both of the first and second strobe source signals are activated.

Abstract: A circuit of a semiconductor memory device may include a delay unit suitable for delaying a column pulse signal, and sequentially generating a first strobe source signal, a column source signal, and a second strobe source signal at a predetermined time interval, and an input/output strobe signal generation unit suitable for generating an input/output strobe signal which is activated during a period in which both of the first and second strobe source signals are activated.

Abstract: Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the to replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed is through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract: A repair circuit includes a normal decoder suitable for decoding partial input addresses of input addresses in response to a first control signal, a comparison unit suitable for comparing the partial input addresses and partial repair addresses of repair addresses in response to a second control signal, and generating a column repair signal when the partial input addresses and the partial repair addresses correspond to each other, and a redundancy decoder suitable for decoding the repair addresses in response to the column repair signal.

Abstract: A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.

Abstract: A semiconductor memory device includes: a core block suitable for storing write data as normal data or a part of combined data according to a data masking signal, and masking information indicating data masking of the combined data; and an error correcting code (ECC) block suitable for performing an ECC decoding operation on the normal data, and bypassing the ECC decoding operation on the combined data according to the masking information, wherein the combined data further includes masked data.

Abstract: A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract: A refresh control circuit of a semiconductor apparatus includes a repair address processing unit configured to compare refresh addresses and repair information, activate a redundant enable signal, and convert the semiconductor apparatus into the same operation state as an initialization state of the repair information in response to activation of a repair initialization signal; a refresh counter configured to count the refresh addresses extended to a signal bit in response to activation of a redundant count enable signal; and a refresh control unit configured to activate the repair initialization signal and the redundant count enable signal when an additional refresh mode is set in response to a refresh command.

Abstract: A semiconductor device may include: a plurality of output paths, which include a plurality of through silicon vias (TSVs), respectively, and suitable for transmission of test confirmation information; an information provider suitable for providing the test confirmation information to the plurality of TSVs; and an output controller suitable for selectively blocking one of the output paths including a failed one among the plurality of TSVs.

Abstract: A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.

Abstract: A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.