Abstract: A refresh control circuit of a semiconductor apparatus includes a repair address processing unit configured to compare refresh addresses and repair information, activate a redundant enable signal, and convert the semiconductor apparatus into the same operation state as an initialization state of the repair information in response to activation of a repair initialization signal; a refresh counter configured to count the refresh addresses extended to a signal bit in response to activation of a redundant count enable signal; and a refresh control unit configured to activate the repair initialization signal and the redundant count enable signal when an additional refresh mode is set in response to a refresh command.

Abstract: A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.

Abstract: A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.

Abstract: A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.

Abstract: A signal transmission/reception system includes a transmission line, a signal transmission circuit configured to generate a transfer signal and transfer the transfer signal through the transmission line, wherein a logic value of the transfer signal is changed whenever a pulse signal is input to the signal transmission circuit, and a signal reception circuit configured to receive the transfer signal through the transmission line and generate a restoration signal using the transfer signal and a delayed transfer signal obtained by delaying the transfer signal.

Abstract: A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.

Abstract: Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

Abstract: A semiconductor integrated circuit includes: a normal fuse cell array programmed with a normal fuse data; a dummy fuse cell array programmed with a verifying fuse data; and a sensor configured to read the verifying fuse data from the dummy fuse cell array and read the normal fuse data from the normal fuse cell array, wherein the normal fuse cell array is configured to be read according to a reading result of the dummy fuse cell array.

Abstract: Provided is a semiconductor device which performs a refresh operation by sequentially counting a refresh address including a main word line address, a mat address, and a sub word line address in order of the main word line address, the mat address, and the sub word line address. The semiconductor device includes a control signal generation unit configured to activate, latch, and output a toggle control signal when a delayed refresh signal is inputted at the initial stage, deactivate and output the toggle control signal after additionally counting a redundancy word line address when counting of the main word line address with respect to the mat address is completed, and then activate, latch, and output the toggle control signal when the delayed refresh signal is inputted.

Abstract: A semiconductor memory apparatus having stacked first and second chips includes a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode, a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode, and a final data determination unit configured to generate a final test signal in response to the first and second chip test signals in the test mode.

Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked, wherein each of the semiconductor chips includes: a first data input/output line configured to transmit data for a first memory bank; a second data input/output line configured to transmit data for a second memory bank; and a data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip.

Abstract: A substrate transfer container comprises a housing including a plurality of substrate slots positioned within a gas chamber having an interior environment. Each substrate slot accommodates a substrate undergoing a substrate manufacturing process, the interior environment of the gas chamber being selectively sealed from an exterior environment. A detection unit at the housing is constructed and arranged to detect an environmental property of the interior environment of the gas chamber, and to generate a detection signal in response. A signal transmission module at the housing is configured to wirelessly transmit a detection signal received from the detection unit.

Abstract: A semiconductor integrated circuit includes: a normal fuse cell array programmed with a normal fuse data; a dummy fuse cell array programmed with a verifying fuse data; and a sensor configured to read the verifying fuse data from the dummy fuse cell array and read the normal fuse data from the normal fuse cell array, wherein the normal fuse cell array is configured to be read according to a reading result of the dummy fuse cell array.

Abstract: A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip.

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract: A signal transmission/reception system includes a transmission line, a signal transmission circuit configured to generate a transfer signal and transfer the transfer signal through the transmission line, wherein a logic value of the transfer signal is changed whenever a pulse signal is input to the signal transmission circuit, and a signal reception circuit configured to receive the transfer signal through the transmission line and generate a restoration signal using the transfer signal and a delayed transfer signal obtained by delaying the transfer signal.

Abstract: A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.

Abstract: A semiconductor integrated circuit includes a first semiconductor chip including a first output circuit which is enabled in a first operation mode and outputs a first output signal and a second output circuit which is enabled in a second operation mode and outputs a second output signal; a second semiconductor chip including a first input circuit which is enabled in the first operation mode and receives the first output signal and a second input circuit which is enabled in the second operation mode and receives the second output signal; and a common through chip via arranged to vertically penetrate through the semiconductor chip, be coupled with the first and second output circuits in one end and coupled with the first and second input circuits in the other end, and interface transfer of the first and second output signals which are enabled in different operation modes, including the first and second operation modes.

Abstract: Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices, and a plurality of through-silicon vias for connecting the master slice to the plurality of slave slices. At least one of the plurality of through-silicon vias may be configured to transmit an operation control signal from the master slice to the plurality of slave slices. The at least one of the plurality of through-silicon vias is configured to be shared by the plurality of slave slices.

Abstract: A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.