Abstract: An apparatus for visualizing a health status information of each individual by using a health space model includes a memory storing a health status information visualization program, and a processor configured to execute the visualization program. The visualization program inputs multidimensional data on the health status of each individual to the health space model to visually display a position of each individual in a two-dimensional health space, the health space model includes a first ordinal regression deep neural network model for outputting a first health status value based on multidimensional data of a first group and a second ordinal regression deep neural network model for outputting a second health status value based on multidimensional data of a second group, and the visualization program displays the health status information in a two-dimensional health space.

Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

Abstract: A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.

Abstract: A semiconductor memory device includes: a plurality of page buffers disposed on a substrate; and a plurality of pads exposed to one surface of a dielectric layer covering the page buffers, and coupled to the respective page buffers. The substrate comprises a plurality of high voltage regions and a plurality of low voltage regions which are alternately disposed in a second direction crossing a first direction. Each of the plurality of page buffers comprises a sensing unit and a bit line select transistor coupled between the sensing unit and the one of the plurality of pads. The bit line select transistors of the plurality of page buffers are disposed in the plurality of high voltage regions, and the plurality of pads are distributed and disposed in a plurality of pad regions which correspond to the high voltage regions and are spaced apart from each other in the second direction.

Abstract: Disclosed are a method for measuring the adhesive strength of a thin film using surface waves, and a computer-readable recording medium having a program for performing same recorded thereon. The method for measuring the adhesive strength of a thin film measures the adhesive strength between a substrate and a thin film by means of an electronic calculator, using sound waves measured from a thin film structure having a thin film formed on a substrate.

Abstract: A semiconductor memory device includes a memory cell array disposed over a substrate extending in a first direction and a second direction intersecting with the first direction in a first semiconductor layer, and including a plurality of cell units and at least two via regions that are arranged in the second direction, wherein a width of each of the at least two via regions in the second direction is a multiple of a width of each of the plurality of cell units in the second direction.

Abstract: A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.

Abstract: A memory device includes an active region with a drain; a plurality of memory blocks arranged in a first direction; and a plurality of pass transistors formed in the active region and sharing the drain, each one of the plurality of pass transistors configured to transfer an operating voltage from the drain to a corresponding one of the plurality of memory blocks in response to a block select signal. The plurality of pass transistors is divided into first pass transistors and second pass transistors. A channel length direction of the first pass transistors and a channel length direction of the second pass transistors are different from each other.

Abstract: A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other.

Abstract: The present invention relates to a semi-automatic scanner for ultrasonic inspection of a branch pipe weld that has a small size and is able to perform an inspection while moving in a state of being attached to a test object by a magnetic force, thereby being applied to fittings having various shapes, such as a branch pipe and an elbow.

Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

Abstract: A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes a first connection pattern, a bit line disposed over the first connection pattern in a vertical direction, and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern so that the bit-line contact pad, and formed as an island when viewed along the vertical direction.

Abstract: A semiconductor memory device includes a memory cell; and a page buffer including a sensing circuit that is coupled to the memory cell through a bit line. The page buffer includes a first transistor included in the sensing circuit; and a second transistor not included in the sensing circuit. A cross-sectional dimension of a first contact which is coupled to the first transistor and a cross-sectional dimension of a second contact which is coupled to the second transistor are different from each other. The cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.

Abstract: A semiconductor memory device may include a memory cell array; and a cache latch circuit that exchanges data with the memory cell array through a plurality of bit lines extended in a second direction crossing a first direction. The memory cell array may include a plurality of cache latches arranged in a plurality of columns in the first direction and in a plurality of rows in the second direction. Each of the cache latches may be coupled to any one of a plurality of input/output (IO) pins. Cache latches coupled to the IO pins at the same time may constitute one IO cache latch unit. The cache latches included in the one IO cache latch unit may be arranged in 2×2 array units.

Abstract: A semiconductor memory device includes a memory cell array; a page buffer circuit including a plurality of page buffers which are coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction; and a cache latch circuit including a plurality of cache latches which are coupled to the plurality of page buffers. The plurality of cache latches have a two-dimensional arrangement in the first direction and the second direction. Among the plurality of cache latches, an even cache latch and an odd cache latch which share a data line and an inverted data line are disposed adjacent to each other in the first direction.

Abstract: A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.

Abstract: A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other.

Abstract: A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.

Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

Abstract: A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.