Abstract: An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.

Abstract: Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.

Abstract: A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

Abstract: A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

Abstract: An upper insulating layer is formed on a semiconductor substrate, the upper insulating layer having an etch selection ratio relative to a lower insulating layer. The upper insulating layer is anisotropically etched by using a contact pad forming mask, to form an opening exposing an upper surface of the semiconductor substrate between conductive patterns on the substrate. The side walls of the upper insulating layer are then isotropically etched, using the above mask again, to expand the size of the opening. The expanded opening is then filled with a conductive layer to form a contact pad to be electrically connected to the semiconductor substrate.

Abstract: The present invention provides a method of forming in an insulating layer a trench that has a minimum feature size exceeding photolithographic resolution limits. The trench is formed by a two-step photolithographic process. The two-step photolithographic process defines a trench mask pattern with a rectangular or/and square shape. The first step photolithographic process defines a plurality of first patterns parallel with each other on the insulating layer. The second step photolithographic process defines a plurality of second patterns on the first patterns and on the insulating layer. The second patterns intersect the first patterns, defining the trench mask pattern. The trench mask pattern is partially etched to form a trench mask pattern with reduced feature sizes exceeding the photolithographic resolution limits.

Abstract: Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.

Abstract: A upper insulating layer is formed on a semiconductor substrate, the upper insulating layer having an etch selection ratio relative to a lower insulating layer. The upper insulating layer is anisotropically etched by using a contact pad forming mask, to form an opening exposing an upper surface of the semiconductor substrate between conductive patterns on the substrate. The side walls of the upper insulating layer are then isotropically etched, using the above mask again, to expand the size of the opening. The expanded opening is then filled with a conductive layer to form a contact pad to be electrically connected to the semiconductor substrate.

Abstract: A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

Abstract: A storage element of a stacked capacitor having a high dielectric film for a semiconductor device and a method of fabricating the same, the storage element having a storage node comprising a bottom polysilicon layer, a barrier metal layer, and a transition metal layer with sidewall spacers formed on the barrier metal layer. The barrier metal layer and sidewall spacers prevent the polysilicon layer from being oxidized. The polysilicon layer is formed to a thickness that determines the height of the storage node. The transition metal layer directly interfacing the high dielectric film is thinly formed to avoid slope etching thereof and thereby prevent electrical bridges or shorts between adjacent storage nodes.

Abstract: A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

Abstract: The size of a pad in the present invention is reduced, thereby preventing a polymer etch-stop, suppressing a short between a gate and a gate conductive layer exposed by the damage of an oxide layer covering the gate conductive layer, and extending a top surface area of a pad beyond the technical limitation of a photo equipment. As a result, it is possible to greatly secure the alignment of a buried contact electrically connected to the pad.

Abstract: A storage element of a stacked capacitor having a high dielectric film for a semiconductor device and a method of fabricating the same, the storage element having a storage node comprising a bottom polysilicon layer, a barrier metal layer, and a transition metal layer with sidewall spacers formed on the barrier metal layer. The barrier metal layer and sidewall spacers prevent the polysilicon layer from being oxidized. The polysilicon layer is formed to a thickness that determines the height of the storage node. The transition metal layer directly interfacing the high dielectric film is thinly formed to avoid slope etching thereof and thereby prevent electrical bridges or shorts between adjacent storage nodes.

Abstract: A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar-shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

Abstract: Self-aligned contact pads in a semiconductor device and a method for forming the same are provided. These self-aligned contact pads can increase the upper surface of the contact pads to increase alignment margins. Portions of the gate mask are undercut, increasing the spaces between the gate structures. As a result, contact pads that are filled in these spaces have an increased upper surface contacting an electrical contact.

Abstract: A method for manufacturing semiconductor devices having a twin well structure in which the N-well and P-well regions of the substrate receive differential processing to set the final planarity of the semiconductor device. The differential processing permits the relative vertical position of the N-well and P-well surfaces to be controlled as needed to reduce the demands on subsequent processing steps. The relative vertical position of the N-well and P-well surfaces are preferentially set to improve the planarity of the semiconductor device during subsequent manufacturing processes, particularly photolithographic and metallization processes.

Abstract: A manufacturing method for a semiconductor memory device including a capacitor having a double fin-shaped structure is provided, wherein a storage electrode is formed by applying a thick planar material capable of being wet-etched between the double fins consisting of conductive layers. The storage electrode is formed by forming a thin, high temperature oxide film having an etching rate which is great. Thus, the resulting memory cell's topography is improved and damage to the storage electrode is decreased.

Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plat poly material is coated and wrapped.

Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three foactors in increasing the effective areas for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterned to selectively remove the storage poly layer, and the spacer makes the storage poly to be remained maximize or be proper by controlling the size thereof; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plate poly material is coated and wraps.

Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a .?.plat.!. .Iadd.plate .Iaddend.poly material is coated and wrapped.