Patents by Inventor Tae-Joo Hwang
Tae-Joo Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11309280Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.Type: GrantFiled: July 8, 2020Date of Patent: April 19, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-hoon Kim, Kil-soo Kim, Kyung-suk Oh, Tae-joo Hwang
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Publication number: 20200343219Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.Type: ApplicationFiled: July 8, 2020Publication date: October 29, 2020Inventors: Yong-hoon KIM, Kil-soo KIM, Kyung-suk OH, Tae-joo HWANG
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Patent number: 10727199Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.Type: GrantFiled: June 7, 2018Date of Patent: July 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-hoon Kim, Kil-soo Kim, Kyung-suk Oh, Tae-joo Hwang
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Patent number: 10665575Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.Type: GrantFiled: September 27, 2019Date of Patent: May 26, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
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Publication number: 20200027862Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-seok SONG, Chan-kyung KIM, Tae-joo HWANG
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Patent number: 10475774Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.Type: GrantFiled: September 18, 2018Date of Patent: November 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
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Publication number: 20190259737Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.Type: ApplicationFiled: September 18, 2018Publication date: August 22, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
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Publication number: 20190148337Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.Type: ApplicationFiled: June 7, 2018Publication date: May 16, 2019Inventors: Yong-hoon KIM, Kil-soo KIM, Kyung-suk OH, Tae-joo HWANG
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Publication number: 20190139939Abstract: A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip including a first circuit surface and a first bottom surface, the first circuit surface having first I/O pads thereon, the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit surface and a second bottom surface; and a second RDL on the second semiconductor chip, the second RDL facing both the first circuit surface and the second circuit surface.Type: ApplicationFiled: January 4, 2019Publication date: May 9, 2019Applicant: Samsung Electronics Co., Ltd.Inventor: Tae Joo HWANG
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Patent number: 10262967Abstract: A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold substrate. The semiconductor chip can include chip pads where a redistribution layer can be on the first surface of the mold substrate, and the redistribution layer can include redistribution lines therein electrically connected to the chip pads and can include a capacitor redistribution line. A capacitor can include a first electrode including a plurality of conductive pillars connected to the capacitor redistribution line. A dielectric layer can be on the first electrode and a second electrode can be on the dielectric layer.Type: GrantFiled: January 11, 2018Date of Patent: April 16, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Joo Hwang, Eun-Seok Song
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Publication number: 20190057949Abstract: A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold substrate. The semiconductor chip can include chip pads where a redistribution layer can be on the first surface of the mold substrate, and the redistribution layer can include redistribution lines therein electrically connected to the chip pads and can include a capacitor redistribution line. A capacitor can include a first electrode including a plurality of conductive pillars connected to the capacitor redistribution line. A dielectric layer can be on the first electrode and a second electrode can be on the dielectric layer.Type: ApplicationFiled: January 11, 2018Publication date: February 21, 2019Inventors: Tae-Joo Hwang, Eun-Seok Song
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Patent number: 10204885Abstract: A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip including a first circuit surface and a first bottom surface, the first circuit surface having first I/O pads thereon, the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit surface and a second bottom surface; and a second RDL on the second semiconductor chip, the second RDL facing both the first circuit surface and the second circuit surface.Type: GrantFiled: April 3, 2017Date of Patent: February 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventor: Tae Joo Hwang
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Patent number: 10020290Abstract: A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.Type: GrantFiled: July 28, 2017Date of Patent: July 10, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeong-Hwan Choe, Tae-Joo Hwang, Tae-Hong Min, Young-Kun Jee, Sang-Uk Han
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Publication number: 20180102339Abstract: A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip including a first circuit surface and a first bottom surface, the first circuit surface having first I/O pads thereon, the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit surface and a second bottom surface; and a second RDL on the second semiconductor chip, the second RDL facing both the first circuit surface and the second circuit surface.Type: ApplicationFiled: April 3, 2017Publication date: April 12, 2018Applicant: Samsung Electronics Co., Ltd.Inventor: Tae Joo HWANG
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Publication number: 20170330862Abstract: A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.Type: ApplicationFiled: July 28, 2017Publication date: November 16, 2017Inventors: Yeong-Hwan CHOE, Tae-Joo HWANG, Tae-Hong MIN, Young-Kun JEE, Sang-Uk HAN
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Patent number: 9721926Abstract: A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one silicon-through-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.Type: GrantFiled: August 13, 2015Date of Patent: August 1, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeong-Hwan Choe, Tae-Joo Hwang, Tae-Hong Min, Young-Kun Jee, Sang-Uk Han
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Patent number: 9685400Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: January 29, 2016Date of Patent: June 20, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
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Patent number: 9484292Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: April 28, 2014Date of Patent: November 1, 2016Assignee: SAMSUNG ELECTRONICS CO. LTD.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
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Publication number: 20160148913Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: ApplicationFiled: January 29, 2016Publication date: May 26, 2016Inventors: Tae-Joo HWANG, Tae-Gyeong CHUNG, Eun-Chul AHN
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Publication number: 20160064357Abstract: A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one silicon-through-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.Type: ApplicationFiled: August 13, 2015Publication date: March 3, 2016Inventors: Yeong-Hwan CHOE, Tae-Joo HWANG, Tae-Hong MIN, Young-Kun JEE, Sang-Uk HAN