Abstract: Provided is a semiconductor device which includes: a channel structure; a gate structure on the channel structure; a 1st source/drain region on the channel structure; a substrate layer below the gate structure; a 1st etch-stop layer below the substrate layer; a backside spacer on side surfaces of the substrate layer and the 1st etch-stop layer; and a backside contact structure on a bottom surface of the 1st source/drain region and a side surface of the backside spacer.

Abstract: Wafer-bonding methods are provided. A wafer-bonding method includes overlaying a first wafer and a second wafer with each other. The first wafer includes a transparent or translucent material having first alignment marks thereon. The second wafer has second alignment marks. The method includes providing light through the first wafer to check alignment of the first alignment marks with the second alignment marks. The method includes bonding the first wafer to the second wafer. Moreover, the method includes removing the transparent or translucent material while the first alignment marks remain bonded to the second wafer.

Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a 1st source/drain region; a 2nd source/drain region; a channel structure connecting the 1st source/drain region to the 2nd source/drain region; a gate structure surrounding the channel structure; a backside contact structure, below the 1st source/drain region, connected to the 1st source/drain region; and a 1st backside spacer at a lateral side of the backside contact structure.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including first and second source/drain regions spaced apart from each other in a horizontal direction, a backside power distribution network structure (BSPDNS), a substrate between the first and second source/drain regions and the BSPDNS, a backside contact that is in the substrate and is overlapped by the first source/drain region, a placeholder that is in the substrate and is overlapped by the second source/drain region, and a cavity in the substrate between the backside contact and the placeholder.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a backside power distribution network structure (BSPDNS), a logic device region and a passive device region on the BSPDNS, a backside insulating layer including a first portion extending between the BSPDNS and the logic device region and a second portion extending between the BSPDNS and the passive device region, the passive device region including a semiconductor layer that is in the backside insulating layer, and a dam separating the first portion of the backside insulating layer from the semiconductor layer of the passive device region.

Abstract: In order to achieve higher contact quality for backside power distribution networks, provided is a backside contact to a semiconductor device having a positive slope and a dielectric sidewall liner, and methods for making the same.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing a substrate structure including a substrate, a bottom insulator and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein and the bottom insulator may include first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region may overlap the power contact; and forming a power rail.

Abstract: Integrated circuit devices are provided. An integrated circuit device includes an insulating layer and a metal via structure that is in the insulating layer. The metal via structure has a lower portion and an upper portion that is narrower than the lower portion. Moreover, the integrated circuit device includes a metal line that is on and electrically connected to the metal via structure. Related methods of forming integrated circuit devices are also provided.

Abstract: Provided is a semiconductor device including at least one front-end-of-line (FEOL) element connected to an interconnect structure, the interconnect structure including: a 1st metal pattern or via structure with a spacer structure on a sidewall thereof; and a 1st interlayer dielectric (ILD) layer formed at sides of the 1st metal pattern or via structure with the spacer structure on the sidewall thereof, wherein the spacer structure includes a dielectric material different from a material included in the 1st ILD layer.

Abstract: A convolution method for high speed deep learning according to the present invention includes (a) a step in which a feature map receiving unit of the convolution system receives a feature map configured by N channels; (b) a step in which a main controller of the convolution system selects a “0”-th channel from the feature map configured by N channels; (c) a step in which the main controller confirms a coordinate in which x, y coordinate is “0”, from the feature map of the “0”-th channel; (d) a coarse step in which a convolution calculating unit of the convolution system performs a convolution operation and a rectified linear unit (ReLU) operation while shifting by 2 in a horizontal direction and a vertical direction in the feature map; (e) a step in which the channel switching unit of the convolution system switches the channel to a subsequent channel when the coarse step is completed for the feature map of the “0”-th channel; (g) a step in which the main controller determines whether the switched channel is

Abstract: A semiconductor device includes a semiconductor substrate including an in-cell area and a scribe lane defining the in-cell area, a first overlay pattern on the semiconductor substrate, and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.

Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.

Abstract: The present invention relates to a method of designing DNA probe chip for room-temperature hybridization in order to solve the solvent evaporation problem occurring when carrying out said hybridization at a high temperature of 40° C.˜50° C. or higher, wherein the method is designed to allow genotyping through hybridizing at a room temperature of 20° C.˜30° C. The method of designing DNA probe chip comprises designing DNA probe to start at ?10˜+5 position that is between ?10 position which is overlapped 10 sequences with primer and +5 position which is 5 sequences far from the 3?-terminal of primer, based on 0 position which is 3?-terminal of primer.

Abstract: Disclosed is a high efficiency video coding (HEVC) encoding device including a candidate group updater configured to select a plurality of representative modes as a candidate group from among intra-prediction modes and update the candidate group using a plurality of minimum modes selected from the candidate group, the plurality of representative modes each representing a range where there is an optimal mode, and an optimal mode selector configured to select any one mode as an optimal mode from among a plurality of minimum modes selected from the updated candidate group.

Abstract: A semiconductor device includes a semiconductor substrate including an in-cell area and a scribe lane defining the in-cell area, a first overlay pattern on the semiconductor substrate, and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.

Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.

Abstract: Disclosed is a high efficiency video coding (HEVC) encoding device including a candidate group updater configured to select a plurality of representative modes as a candidate group from among intra-prediction modes and update the candidate group using a plurality of minimum modes selected from the candidate group, the plurality of representative modes each representing a range where there is an optimal mode, and an optimal mode selector configured to select any one mode as an optimal mode from among a plurality of minimum modes selected from the updated candidate group.

Abstract: The method may include forming a plurality of fins on a substrate with first and second regions, forming a photoresist pattern to expose the fins of the first region, forming a material layer to cover the fins of first region and the photoresist pattern, chemically reacting the photoresist pattern the material layer to form a supplemental film on a side surface of the photoresist pattern, performing an ion implantation process using the photoresist pattern and the supplemental film as a ion injection mask to form impurity layers in the fins of the first region.

Abstract: In a method, an isolation layer pattern is formed on a substrate to define first and second active fins. An ARC layer is formed on the isolation layer pattern to at least partially cover sidewalls of the first and second active fins. A level of a top surface of the ARC layer is equal to or less than, and equal to or greater than half of, those of the first and second active fins. A photoresist layer is formed on the first and second active fins and the ARC layer. A portion of the photoresist layer is removed to form a photoresist pattern covering the first active fin and exposing the second active fin. A portion of the ARC layer under the removed portion of the photoresist layer is removed to form an ARC layer pattern. Impurities are implanted into the exposed second active fin to form an impurity region.

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.