Patents by Inventor Tahir Ghani

Tahir Ghani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200251387
    Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
    Type: Application
    Filed: March 16, 2020
    Publication date: August 6, 2020
    Inventors: Mark T. BOHR, Tahir GHANI, Nadia M. RAHHAL-ORABI, Subhash M. JOSHI, Joseph M. STEIGERWALD, Jason W. KLAUS, Jack HWANG, Ryan MACKIEWICZ
  • Patent number: 10732217
    Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Kaan Oguz, Christopher J. Wiegand, Mark L. Doczy, Brian S. Doyle, MD Tofizur Rahman, Oleg Golonzka, Tahir Ghani
  • Publication number: 20200235246
    Abstract: Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Van H. Le, Li Huey Tan, Tristan A. Tronic, Benjamin Chu-Kung, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200227539
    Abstract: Techniques and mechanisms for providing functionality of a non-planar device which includes a semiconductor body disposed on a dielectric layer and over an underlying subfin region. In an embodiment, the dielectric layer is disposed between, and adjoins each of, a first semiconductor material of the subfin region and a second semiconductor material of semiconductor body. The dielectric layer is an artefact of fabrication processing wherein an epitaxy of the semiconductor body is grown horizontally along a length of the subfin region. During such epitaxial growth, the dielectric layer prevents vertical growth of the second semiconductor material from the subfin region. Moreover, at least a portion of a dummy gate determines a shape of the semiconductor body. In another embodiment, formation of the semiconductor body is preceded by an etching to remove a section of a fin portion which is disposed over the subfin region.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Sean Ma, Nicholas Minutillo, Tahir Ghani, Matthew V. Metz, Cheng-Ying Huang, Anand S. Murthy
  • Publication number: 20200227472
    Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: Kevin J. LEE, Tahir GHANI, Joseph M. STEIGERWALD, John H. EPPLE, Yih WANG
  • Publication number: 20200227535
    Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 16, 2020
    Applicant: INTEL CORPORATION
    Inventors: Seung Hoon Sung, Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200220024
    Abstract: A back-gated thin-film transistor (TFT) includes a gate electrode, a gate dielectric on the gate electrode, an active layer on the gate dielectric and having source and drain regions and a semiconductor region physically connecting the source and drain regions, a capping layer on the semiconductor region, and a charge trap layer on the capping layer. In an embodiment, a memory cell includes this back-gated TFT and a capacitor, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline, the capacitor having a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In another embodiment, an embedded memory includes wordlines extending in a first direction, bitlines extending in a second direction crossing the first direction, and several such memory cells at crossing regions of the wordlines and bitlines.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Cory E. Weber, Sean T. Ma, Tahir Ghani, Shriram Shivaraman, Gilbert Dewey
  • Publication number: 20200220014
    Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.
    Type: Application
    Filed: September 27, 2017
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Karthik Jambunathan, Biswajeet Guha, Anupama Bowonder, Anand S. Murthy, Tahir Ghani
  • Publication number: 20200219975
    Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Inventors: Cory BOMBERGER, Anand MURTHY, Anupama BOWONDER, Aaron BUDREVICH, Tahir GHANI
  • Publication number: 20200219978
    Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Inventors: Leonard P. GULER, Biswajeet GUHA, Tahir GHANI, Swaminathan SIVAKUMAR
  • Publication number: 20200220016
    Abstract: Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.
    Type: Application
    Filed: January 4, 2019
    Publication date: July 9, 2020
    Inventors: Leonard GULER, Nick LINDERT, Biswajeet GUHA, Swaminathan SIVAKUMAR, Tahir GHANI
  • Publication number: 20200219990
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Inventors: Biswajeet GUHA, Dax M. CRUM, Stephen M. CEA, Leonard P. GULER, Tahir GHANI
  • Publication number: 20200219997
    Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Inventors: Rishabh MEHANDRU, Tahir GHANI, Stephen CEA, Biswajeet GUHA
  • Publication number: 20200212039
    Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Tahir GHANI, Salman LATIF, Chanaka D. MUNASINGHE
  • Publication number: 20200212200
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Application
    Filed: February 25, 2020
    Publication date: July 2, 2020
    Inventors: Tahir GHANI, Byron HO, Michael L. HATTENDORF, Christopher P. AUTH
  • Patent number: 10700178
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 10692973
    Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Benjamin Chu-Kung, Seung Hoon Sung, Jack T. Kavalieros, Tahir Ghani, Harold W. Kennel
  • Patent number: 10692974
    Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Prashant Majhi, Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Aravind S. Killampalli, Mark R. Brazier, Jaya P. Gupta
  • Publication number: 20200194309
    Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Inventors: Oleg GOLONZKA, Swaminathan SIVAKUMAR, Charles H. WALLACE, Tahir GHANI
  • Publication number: 20200194434
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Juan G. ALZATE VINASCO, Abhishek A. SHARMA, Fatih HAMZAOGLU, Bernhard SELL, Pei-Hua WANG, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Chieh-Jen KU, Travis W. LAJOIE, Umut ARSLAN