Patents by Inventor Tahir Ghani

Tahir Ghani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12016170
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.
    Type: Grant
    Filed: March 22, 2023
    Date of Patent: June 18, 2024
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Curtis W. Ward, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 12014959
    Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: June 18, 2024
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Biswajeet Guha, Mark Armstrong, Tahir Ghani, William Hsu
  • Patent number: 12002810
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Dax M. Crum, Biswajeet Guha, Leonard Guler, Tahir Ghani
  • Publication number: 20240178226
    Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.
    Type: Application
    Filed: February 9, 2024
    Publication date: May 30, 2024
    Inventors: Leonard P. GULER, Michael K. HARPER, William HSU, Biswajeet GUHA, Tahir GHANI, Niels ZUSSBLATT, Jeffrey Miles TAN, Benjamin KRIEGEL, Mohit K. HARAN, Reken PATEL, Oleg GOLONZKA, Mohammad HASAN
  • Patent number: 11996362
    Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Mark T. Bohr, Tahir Ghani, Rishabh Mehandru, Ranjith Kumar
  • Patent number: 11997847
    Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Shriram Shivaraman, Yih Wang, Tahir Ghani, Jack T. Kavalieros
  • Patent number: 11996447
    Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 11990472
    Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Michael K. Harper, William Hsu, Biswajeet Guha, Tahir Ghani, Niels Zussblatt, Jeffrey Miles Tan, Benjamin Kriegel, Mohit K. Haran, Reken Patel, Oleg Golonzka, Mohammad Hasan
  • Patent number: 11991873
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
  • Publication number: 20240164080
    Abstract: Embodiments disclosed herein include forksheet transistor devices with depopulated channels. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to a first edge of the backbone. The first vertical stack of semiconductor channels includes first semiconductor channels and a second semiconductor channel over or beneath the first semiconductor channels. A concentration of a dopant in the first semiconductor channels is less than a concentration of the dopant in the second semiconductor channel. A second transistor device includes a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge.
    Type: Application
    Filed: October 2, 2023
    Publication date: May 16, 2024
    Inventors: Peng ZHENG, Varun MISHRA, Harold W. KENNEL, Eric A. KARL, Tahir GHANI
  • Patent number: 11984449
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Cory Bomberger, Anand Murthy, Stephen Cea, Biswajeet Guha, Anupama Bowonder, Tahir Ghani
  • Publication number: 20240154037
    Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 9, 2024
    Inventors: Leonard P. GULER, Tahir GHANI, Charles H. WALLACE, Mohit K. HARAN, Mohammad HASAN, Aryan NAVABI-SHIRAZI, Allen B. GARDINER
  • Publication number: 20240153956
    Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Inventors: Seung Hoon SUNG, Cheng-Ying HUANG, Marko RADOSAVLJEVIC, Christopher M. NEUMANN, Susmita GHOSE, Varun MISHRA, Cory WEBER, Stephen M. CEA, Tahir GHANI, Jack T. KAVALIEROS
  • Publication number: 20240153995
    Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
    Type: Application
    Filed: November 30, 2023
    Publication date: May 9, 2024
    Inventors: Seiyon KIM, Kelin J. KUHN, Tahir GHANI, Anand S. MURTHY, Mark ARMSTRONG, Rafael RIOS, Abhijit Jayant PETHE, Willy RACHMADY
  • Patent number: 11978804
    Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Yih Wang
  • Publication number: 20240145549
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Inventors: Siddharth CHOUKSEY, Glenn GLASS, Anand MURTHY, Harold KENNEL, Jack T. KAVALIEROS, Tahir GHANI, Ashish AGRAWAL, Seung Hoon SUNG
  • Publication number: 20240145568
    Abstract: Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 2, 2024
    Inventors: Leonard P. GULER, Charles H. WALLACE, Tahir GHANI
  • Publication number: 20240145471
    Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR
  • Publication number: 20240145592
    Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Anand S. MURTHY, Daniel Boune AUBERTINE, Tahir GHANI, Abhijit Jayant PETHE
  • Publication number: 20240120335
    Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Inventors: Sudipto NASKAR, Biswajeet GUHA, William HSU, Bruce BEATTIE, Tahir GHANI