Patents by Inventor Tahir Ghani

Tahir Ghani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10388764
    Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Matthew V. Metz, Gilbert Dewey, Willy Rachmady, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10388800
    Abstract: A thin film transistor (TFT) device is provided, where the TFT may include a plurality of stacked structures comprising metal oxide. In an example, any two adjacent structures of the plurality of stacked structures may be separated by a corresponding intervening structure. In an example, the TFT may also include gate dielectric material on at least a first side and a second side of the plurality of stacked structures. In an example, the TFT may further include a gate electrode comprising a first section and a second section, where the first and second sections of the gate electrode may be respectively on the first side and the second side of the plurality of stacked structures.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack Kavalieros, Tahir Ghani
  • Publication number: 20190252525
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Inventors: Rishabh MEHANDRU, Patrick MORROW, Ranjith KUMAR, Cory E. WEBER, Seiyon KIM, Stephen M. CEA, Tahir GHANI
  • Publication number: 20190245060
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Tahir GHANI, Byron HO, Michael L. HATTENDORF, Christopher P. AUTH
  • Patent number: 10373977
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 6, 2019
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Chandra S. Mohapatra, Karthik Jambunathan, Gilbert Dewey, Willy Rachmady
  • Publication number: 20190221641
    Abstract: Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 18, 2019
    Applicant: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Nabil G. Mistkawi, Karthik Jambunathan, Tahir Ghani
  • Publication number: 20190214461
    Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: Seiyon KIM, Kelin J. KUHN, Tahir GHANI, Anand S. MURTHY, Mark ARMSTRONG, Rafael RIOS, Abhijit Jayant PETHE, Willy RACHMADY
  • Publication number: 20190214479
    Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 11, 2019
    Applicant: INTEL CORPORATION
    Inventors: KARTHIK JAMBUNATHAN, GLENN A. GLASS, ANAND S. MURTHY, JACK T. KAVALIEROS, SEUNG HOON SUNG, BENJAMIN CHU-KUNG, TAHIR GHANI
  • Patent number: 10340374
    Abstract: Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10340185
    Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Oleg Golonzka, Swaminathan Sivakumar, Charles H. Wallace, Tahir Ghani
  • Patent number: 10340445
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Publication number: 20190198658
    Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.
    Type: Application
    Filed: September 29, 2016
    Publication date: June 27, 2019
    Applicant: INTEL CORPORATION
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Anand S. Murthy, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz, Sean T. Ma
  • Publication number: 20190189755
    Abstract: Techniques are disclosed for forming transistors including source and drain (S/D) regions employing double-charge dopants. As can be understood based on this disclosure, the use of double-charge dopants for group IV semiconductor material (e.g., Si, Ge, SiGe) either alone or in combination with single-charge dopants (e.g., P, As, B) can decrease the energy barrier at the semiconductor/metal interface between the source and drain regions (semiconductor) and their respective contacts (metal), thereby improving (by reducing) contact resistance at the S/D locations. In some cases, the double-charge dopants may be provided in a top or cap S/D portion of a given S/D region, for example, so that the double-charge doped S/D material is located at the interface of that S/D region and the corresponding contact. The double-charge dopants can include sulfur (S), selenium (Se), and/or tellurium (Te). Other suitable group IV material double-charge dopants will be apparent in light of this disclosure.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Publication number: 20190189794
    Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.
    Type: Application
    Filed: February 23, 2019
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: CHANDRA S. MOHAPATRA, ANAND S. MURTHY, GLENN A. GLASS, TAHIR GHANI, WILLY RACHMADY, JACK T. KAVALIEROS, GILBERT DEWEY, MATTHEW V. METZ, HAROLD W. KENNEL
  • Publication number: 20190189785
    Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.
    Type: Application
    Filed: September 28, 2016
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: KARTHIK JAMBUNATHAN, GLENN A. GLASS, ANAND S. MURTHY, JACK T. KAVALIEROS, SEUNG HOON SUNG, BENJAMIN CHU-KUNG, TAHIR GHANI
  • Publication number: 20190189749
    Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.
    Type: Application
    Filed: September 28, 2016
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: Benjamin Chu-Kung, Van Le, Seung Hoon Sung, Jack Kavalieros, Ashish Agrawal, Harold Kennel, Siddharth Chouksey, Anand Murthy, Tahir Ghani, Glenn Glass, Cheng-Ying Huang
  • Patent number: 10326075
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Patent number: 10319812
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Milton Clair Webb, Mark Bohr, Tahir Ghani, Szuya S. Liao
  • Publication number: 20190172941
    Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.
    Type: Application
    Filed: July 2, 2016
    Publication date: June 6, 2019
    Applicant: Intel Corporation
    Inventors: Willy RACHMADY, Sanaz K. GARDNER, Chandra S. MOHAPATRA, Matthew V. METZ, Gilbert DEWEY, Sean T. MA, Jack T. KAVALIEROS, Anand S. MURTHY, Tahir GHANI
  • Publication number: 20190164808
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 30, 2019
    Inventors: Michael L. HATTENDORF, Curtis WARD, Heidi M. MEYER, Tahir GHANI, Christopher P. AUTH