Abstract: An integrated circuit die includes a first conductive structure for an input of a capacitively coupled device, a second conductive structure aligned with the first conductive structure for a signal to be capacitively coupled to the input of the capacitively coupled device, a first insulator material disposed between the first conductive structure and the second conductive structure, wherein the first insulator material comprises high gain insulator material, and a cooling structure operable to remove heat from the capacitively coupled device to achieve an operating temperature at or below 0° C. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a capacitor in the back-side layers of an IC die may comprise any type of solid-state electrolyte material disposed between electrodes of the capacitor. Another embodiment of a capacitor anywhere in an IC die may include one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride between electrodes of the capacitor. Other embodiments are disclosed and claimed.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines on a same level and along a same direction, a first one of the plurality of conductive lines having a first width and a first composition, and a second one of the plurality of conductive lines having a second width and a second composition. The second width greater than the first width, and the second composition is different than the first composition. The integrated circuit structure also includes an inter-layer dielectric (ILD) structure having portions between adjacent ones of the plurality of conductive lines.

Abstract: IC devices with angled interconnects are disclosed herein. An interconnect, specifically a trench or line interconnect, is referred to as an “angled interconnect” if the interconnect is neither perpendicular nor parallel to any edges of front or back faces of the support structure, or if the interconnect is not parallel or perpendicular to interconnect in another region of an interconnect layer. Angled interconnects may be used to decrease the area of pitch transition regions. Angled interconnects may also be used to decrease the area of pitch offset regions.

Abstract: An integrated circuit (IC) die includes a plurality of front-side metallization layers including a first front-side metallization layer and one or more additional front-side metallization layers, a plurality of back-side metallization layers formed on the plurality front side metallization layers including a first back-side metallization layer and one or more additional back-side metallization layers, wherein the first front-side metallization layer is proximate to the first back-side metallization layer, and a vertical metallization structure formed through at least the first front-side metallization layer and the first back-side metallization layer, wherein the vertical metallization structure electrically connects a first metallization structure on one of the one or more additional front-side metallization layers to a second metallization structure on one of the one or more additional back-side metallization layers. Other embodiments are disclosed and claimed.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines along a same direction, one of the conductive lines having a break therein. An inter-layer dielectric (ILD) structure has portions between adjacent ones of the plurality of conductive lines and has a dielectric plug portion in a location of the break in the one of the conductive lines. The dielectric plug portion of the ILD structure is continuous with one or more of the portions of the ILD structure between adjacent ones of the plurality of conductive lines. The dielectric plug portion of the ILD structure has an inwardly tapering profile from top to bottom.

Abstract: An integrated circuit (IC) die includes a first layer with conductive structures formed in a interlayer dielectric (ILD) material, with a portion of the conductive structures at a first surface of the first layer, a self-alignment layer in contact with non-conductive regions at the first surface of the first layer, a second layer with ILD material in contact with the self-alignment layer and the portion of the conductive structures at the first surface of the first layer, and conductive vias through the self-alignment layer and the second layer in contact with the portion of the conductive structures at the first surface of the first layer. The self-alignment layer may include a first material where the self-alignment layer is in contact with the conductive vias and a second material where the self-alignment layer is not in contact with the conductive vias. Other embodiments are disclosed and claimed.

Abstract: Mushroomed via structures for trench contact or gate contact are described. In an example, an integrated circuit structure includes a trench contact structure over an epitaxial source or drain structure. A dielectric layer is over the trench contact structure. A trench contact via is in an opening in the dielectric layer, the trench contact via in contact with the trench contact structure. A trench contact via extension is on the trench contact via. The trench contact via extension above the dielectric layer and extending laterally beyond the trench contact via.

Abstract: An example IC device formed using trim patterning as described herein may include a support structure, a first elongated structure (e.g., a first fin or nanoribbon) and a second elongated structure (e.g., a second fin or nanoribbon), proximate to an end of the first elongated structure. An angle between a projection of the first elongated structure on the support structure and an edge of the support structure may be between about 5 and 45 degrees, while an angle between a projection of the second elongated structure on the support structure and the edge of the support structure may be less than about 15 degrees.

Abstract: An integrated circuit device includes a first IC die with a first front surface, a first back surface, and a first side surface along opposed edges of the first front surface and the first back surfaces of the first IC die, a second IC die with a second front surface, a second back surface, and a second side surface along opposed edges of the second front surface and second back surface of the second IC die, a substrate coupled to the first side surface of the first IC die and the second side surface of the second IC die, and fill material between one of the first front surface and the first back surface of the first IC die and one of the second front surface and second back surface of the second IC die. Other embodiments are disclosed and claimed.

Abstract: Various arrangements for IC devices implementing memory with one access transistor for multiple capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N capacitors coupled to the access transistor. A portion of the capacitors are formed in one or more layers above the access transistor, and a portion of the capacitors are formed in one or more layers below the access transistor. The capacitors in a particular memory unit may be coupled to a single via or to individual vias. In some embodiments, some of the vias are backside vias.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Abstract: An integrated circuit (IC) die includes a plurality of varactor devices, where at least one varactor of the plurality of varactor devices comprises a first electrode, a second electrode, and a multi-layer stack of ferroelectric material (e.g., ferroelectric variable capacitance material) disposed between the first and second electrodes. Other embodiments are disclosed and claimed.

Abstract: Integrated circuit structures having channel cap reduction, and methods of fabricating integrated circuit structures having channel cap reduction, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first end and a second end. A dielectric cap has a first portion vertically over the first end of the stack of nanowires and has a second portion vertically over the second end of the stack of nanowires. The dielectric cap is not vertically over a location between the first end and the second end of the stack of nanowires. A gate electrode is over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap. A gate dielectric structure is between the gate electrode and the stack of nanowires.

Abstract: An embodiment of an integrated circuit (IC) device may include a plurality of layers of wide bandgap (WBG)-based circuitry and a plurality of layers of silicon (Si)-based circuitry monolithically bonded to the plurality of layers of WBG-based circuitry, with one or more electrical connections between respective WBG-based circuits in the plurality of layers of WBG-based circuitry and Si-based circuits in the plurality of layers of Si-based circuitry. In some embodiments, a wafer-scale WBG-based IC is hybrid bonded or layer transfer bonded to a wafer-scale Si-based IC. Other embodiments are disclosed and claimed.

Abstract: Integrated circuit structures having trench contact depopulation structures, and methods of fabricating integrated circuit structures having trench contact depopulation structures, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate stack is over the vertical stack of horizontal nanowires. A dielectric trench structure is adjacent to the gate stack. A dielectric sidewall spacer is between the gate stack and the dielectric trench structure. A dielectric gate cut plug is extending through the gate stack, the dielectric sidewall spacer, and the dielectric trench structure.

Abstract: Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

Abstract: Described herein are full wafer devices that include passive devices formed in a power delivery structure. Power is delivered to the full wafer device on a backside of the full wafer device. A passive device in a backside layer is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device.