Patents by Inventor Tai-Su Park
Tai-Su Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6900090Abstract: A device isolation structure in a semiconductor device and a method for fabricating the same are disclosed. A trench is formed in a semiconductor substrate to confine a plurality of active regions, an insulating material is deposited to fill the trench and the insulating material having a portion extending from the trench to above the semiconductor substrate, and a trench oxidation preventive film is formed on the insulating material. The semiconductor device preferably further includes a gate line extending in one direction on the semiconductor substrate having the trench oxidation-preventive film, and a sidewall spacer formed a sidewall of the gate line, wherein the trench oxidation-preventive film is disposed on the insulating material and disposed under the gate line and the sidewall spacer.Type: GrantFiled: July 21, 2003Date of Patent: May 31, 2005Assignee: Samsung Electronics Co., LTDInventor: Tai-Su Park
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Publication number: 20050056888Abstract: Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.Type: ApplicationFiled: August 11, 2004Publication date: March 17, 2005Inventors: Jae-Man Youn, Dong-gun Park, Gyo-young Jin, Yoshida Makoto, Tai-su Park
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Patent number: 6717231Abstract: Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g.Type: GrantFiled: August 20, 2002Date of Patent: April 6, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-eui Kim, Keum-joo Lee, In-seak Hwang, Young-sun Koh, Dong-ho Ahn, Moon-han Park, Tai-su Park
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Publication number: 20040018676Abstract: A device isolation structure in a semiconductor device and a method for fabricating the same are disclosed. A trench is formed in a semiconductor substrate to confine a plurality of active regions, an insulating material is deposited to fill the trench and the insulating material having a portion extending from the trench to above the semiconductor substrate, and a trench oxidation preventive film is formed on the insulating material. The semiconductor device preferably further includes a gate line extending in one direction on the semiconductor substrate having the trench oxidation-preventive film, and a sidewall spacer formed a sidewall of the gate line, wherein the trench oxidation-preventive film is disposed on the insulating material and disposed under the gate line and the sidewall spacer.Type: ApplicationFiled: July 21, 2003Publication date: January 29, 2004Inventor: Tai-Su Park
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Patent number: 6645866Abstract: A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.Type: GrantFiled: December 16, 2002Date of Patent: November 11, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-su Park, Kyung-won Park, Jung-woo Park, Won-sang Song
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Patent number: 6627514Abstract: A semiconductor device having a Y-shaped isolation layer and a method for manufacturing the same are provided. The semiconductor device includes a Y-shaped isolation layer, which comprises side walls characterized by first and second slopes on the sides of the isolation layer. The method for manufacturing the isolation layer includes the step of forming a trench in a semiconductor substrate using a photoresist pattern as an etching mask. Next, a thermal oxide film is formed on the surface of the semiconductor substrate, and then a thin nitride liner is formed on the thermal oxide film. The nitride liner prevents oxidation of the side wall of the trench and also acts as a planarization stop layer. Thereafter, a gap-filling isolation layer is formed to fill the trench such that the nitride liner is separated or thinner at the upper corners of the trench. Next, the gap-filling isolation layer is planarized using the nitride liner as a planarization stop layer.Type: GrantFiled: November 10, 2000Date of Patent: September 30, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-su Park, Kyung-won Park, Sung-jin Kim
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Patent number: 6617662Abstract: A device isolation structure in a semiconductor device and a method for fabricating the same are disclosed. A trench is formed in a semiconductor substrate to confine a plurality of active regions, an insulating material is deposited to fill the trench and the insulating material having a portion extending from the trench to above the semiconductor substrate, and a trench oxidation preventive film is formed on the insulating material. The semiconductor device preferably further includes a gate line extending in one direction on the semiconductor substrate having the trench oxidation-preventive film, and a sidewall spacer formed a sidewall of the gate line, wherein the trench oxidation-preventive film is disposed on the insulating material and disposed under the gate line and the sidewall spacer.Type: GrantFiled: September 27, 2001Date of Patent: September 9, 2003Assignee: Samsung Electronics, Co., LTDInventor: Tai-Su Park
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Publication number: 20030104677Abstract: A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.Type: ApplicationFiled: December 16, 2002Publication date: June 5, 2003Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Tai-Su Park, Kyung-Won Park, Jung-Woo Park, Won-Sang Song
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Patent number: 6537914Abstract: Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.Type: GrantFiled: May 12, 2000Date of Patent: March 25, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-su Park, Moon-han Park, Kyung-won Park, Han-sin Lee, Jung-yup Kim, Chang-ki Hong, Ho-kyu Kang
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Publication number: 20030038334Abstract: Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g.Type: ApplicationFiled: August 20, 2002Publication date: February 27, 2003Inventors: Sung-eui Kim, Keum-joo Lee, In-seak Hwang, Young-sun Koh, Dong-ho Ahn, Moon-han Park, Tai-su Park
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Patent number: 6511888Abstract: A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.Type: GrantFiled: October 27, 2000Date of Patent: January 28, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-su Park, Kyung-won Park, Jung-woo Park, Won-sang Song
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Patent number: 6482715Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.Type: GrantFiled: August 13, 2001Date of Patent: November 19, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-su Park, Ho-kyu Kang, Dong-ho Ahn, Moon-han Park
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Patent number: 6465866Abstract: A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.Type: GrantFiled: July 23, 2001Date of Patent: October 15, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-su Park, Moon-han Park, Kyung-won Park, Han-sin Lee
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Patent number: 6461937Abstract: Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g.Type: GrantFiled: January 7, 2000Date of Patent: October 8, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-eui Kim, Keum-joo Lee, In-seak Hwang, Young-sun Koh, Dong-ho Ahn, Moon-han Park, Tai-su Park
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Publication number: 20020135025Abstract: A device isolation structure in a semiconductor device and a method for fabricating the same are disclosed. A trench is formed in a semiconductor substrate to confine a plurality of active regions, an insulating material is deposited to fill the trench and the insulating material having a portion extending from the trench to above the semiconductor substrate, and a trench oxidation preventive film is formed on the insulating material. The semiconductor device preferably further includes a gate line extending in one direction on the semiconductor substrate having the trench oxidation-preventive film, and a sidewall spacer formed a sidewall of the gate line, wherein the trench oxidation-preventive film is disposed on the insulating material and disposed under the gate line and the sidewall spacer.Type: ApplicationFiled: September 27, 2001Publication date: September 26, 2002Applicant: Samsung Electronics Co., Ltd.Inventor: Tai-Su Park
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Publication number: 20020076900Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.Type: ApplicationFiled: August 13, 2001Publication date: June 20, 2002Inventors: Tai-Su Park, Ho-Kyu Kang, Dong-Ho Ahn, Moon-Han Park
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Publication number: 20020003275Abstract: A shallow trench type (STI) type semiconductor device employs an etch-stop layer pull-pack approach and a liner as an oxygen barrier, enhancing stability of gate insulation and reliability of transistor operation, wherein a trench sidewall thermal oxide layer with a thickness of 20 Å-140 Å is formed between silicon substrate and the liner, controlling the sidewall liner tension that acts on the substrate. This makes it possible to control the thickness of a gate insulating layer adjacent to a trench to a value equal to or greater than a value in the middle of an active region. Further, a corner adjacent to the trench is rounded to increase the voltage handling capability of device.Type: ApplicationFiled: July 6, 2001Publication date: January 10, 2002Inventors: Keum-Joo Lee, Tai-Su Park, Young-min Kwon, Bong-Ho Moon, In-Seak Hwang, Chang-Lyoung Song
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Patent number: 6331469Abstract: A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.Type: GrantFiled: October 10, 2000Date of Patent: December 18, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-su Park, Moon-han Park, Kyung-won Park, Han-sin Lee
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Publication number: 20010041421Abstract: A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.Type: ApplicationFiled: July 23, 2001Publication date: November 15, 2001Inventors: Tai-Su Park, Moon-Han Park, Kyung-Won Park, Han-Sin Lee
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Patent number: 6258726Abstract: A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.Type: GrantFiled: October 5, 1999Date of Patent: July 10, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-Su Park, Yu-gyun Shin, Han-sin Lee, Kyung-won Park