Patents by Inventor Taiji Ema

Taiji Ema has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991707
    Abstract: A semiconductor device is disclosed. A gate electrode is provided above a semiconductor substrate. A sidewall insulation film is provided to the gate electrode. Source and drain regions are provided in the substrate and contain first conductive impurities. A first semiconductor region is provided in the substrate, is on a source region side, and has a concentration of the first conductive impurities lower than the source region. A second semiconductor region is provided in the substrate, is on a drain region side, and has a concentration of the first conductive impurities lower than the drain and first semiconductor regions. A channel region is provided between the first and second semiconductor regions. A third semiconductor region is provided under the channel region, and includes second conductive impurities higher in concentration than the channel region. Information is stored by accumulating charges in the sidewall insulation film.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: April 27, 2021
    Assignee: United Semiconductor Japan Co., Ltd.
    Inventors: Taiji Ema, Makoto Yasuda
  • Patent number: 10878927
    Abstract: A control circuit controls a column decoder and a row decoder to perform reprogramming where, before the count of reprogramming operations involving erasures, each targeting one of a plurality of memory cells included in a memory cell array, reaches a predetermined number, a first extent (e.g. a sub-block) including the targeted memory cell and being smaller than the entire extent of the memory cell array is used as the unit of reprogramming, and when the count of reprogramming operations reaches the predetermined number, a second extent (e.g. the memory cell array corresponding to one sector) including the targeted memory cell and being larger than the first extent is used as the unit of reprogramming, and resets the count of reprogramming operations each time it reaches the predetermined number.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 29, 2020
    Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.
    Inventors: Taiji Ema, Makoto Yasuda
  • Patent number: 10840323
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: November 17, 2020
    Assignee: United Semiconductor Japan Co., Ltd.
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasuda
  • Patent number: 10818594
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: October 27, 2020
    Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 10741699
    Abstract: A semiconductor device includes a gate insulator layer above a semiconductor substrate, a gate electrode above the gate insulating layer, a sidewall insulator layer on sidewalls of the gate electrode and above the substrate, source and drain regions within the substrate on both sides of the gate electrode, a first region within the substrate below a part of the sidewall insulator layer closer to the source region and having an impurity concentration lower than the source region, a second region provided within the substrate below a part of the sidewall insulator layer closer to the drain region and having an impurity concentration lower than the drain region, a channel region provided within the substrate between the first and second regions, and a third region within the substrate below the channel region and including impurities of a different type and having an impurity concentration higher than the channel region.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 11, 2020
    Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.
    Inventors: Taiji Ema, Makoto Yasuda
  • Patent number: 10720489
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 21, 2020
    Assignee: United Semiconductor Japan Co., Ltd.
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasuda
  • Patent number: 10510824
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasuda
  • Publication number: 20190371419
    Abstract: A control circuit controls a column decoder and a row decoder to perform reprogramming where, before the count of reprogramming operations involving erasures, each targeting one of a plurality of memory cells included in a memory cell array, reaches a predetermined number, a first extent (e.g. a sub-block) including the targeted memory cell and being smaller than the entire extent of the memory cell array is used as the unit of reprogramming, and when the count of reprogramming operations reaches the predetermined number, a second extent (e.g. the memory cell array corresponding to one sector) including the targeted memory cell and being larger than the first extent is used as the unit of reprogramming, and resets the count of reprogramming operations each time it reaches the predetermined number.
    Type: Application
    Filed: May 2, 2019
    Publication date: December 5, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda
  • Publication number: 20190363195
    Abstract: A semiconductor device includes a gate insulator layer above a semiconductor substrate, a gate electrode above the gate insulating layer, a sidewall insulator layer on sidewalls of the gate electrode and above the substrate, source and drain regions within the substrate on both sides of the gate electrode, a first region within the substrate below a part of the sidewall insulator layer closer to the source region and having an impurity concentration lower than the source region, a second region provided within the substrate below a part of the sidewall insulator layer closer to the drain region and having an impurity concentration lower than the drain region, a channel region provided within the substrate between the first and second regions, and a third region within the substrate below the channel region and including impurities of a different type and having an impurity concentration higher than the channel region.
    Type: Application
    Filed: February 12, 2019
    Publication date: November 28, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda
  • Publication number: 20190326386
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasudo
  • Publication number: 20190326385
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasudo
  • Publication number: 20190267320
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 10373952
    Abstract: A semiconductor device includes first and second transistors connected to the same power supply. Each of the first and second transistors includes, under a channel region of a low concentration provided between a source region and a drain region of a first conductivity type, an impurity region of a second conductivity type having a higher concentration. The thickness of the gate insulating film in one of the first and second transistors is made larger than the thickness of the gate insulating film in the other one.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 6, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazushi Fujita
  • Publication number: 20190237473
    Abstract: A semiconductor device is disclosed. A gate electrode is provided above a semiconductor substrate. A sidewall insulation film is provided to the gate electrode. Source and drain regions are provided in the substrate and contain first conductive impurities. A first semiconductor region is provided in the substrate, is on a source region side, and has a concentration of the first conductive impurities lower than the source region. A second semiconductor region is provided in the substrate, is on a drain region side, and has a concentration of the first conductive impurities lower than the drain and first semiconductor regions. A channel region is provided between the first and second semiconductor regions. A third semiconductor region is provided under the channel region, and includes second conductive impurities higher in concentration than the channel region. Information is stored by accumulating charges in the sidewall insulation film.
    Type: Application
    Filed: November 27, 2018
    Publication date: August 1, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda
  • Patent number: 10354953
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 16, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 10192866
    Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 29, 2019
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
  • Patent number: 10090201
    Abstract: A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: October 2, 2018
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
  • Publication number: 20180277478
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 27, 2018
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Publication number: 20180277618
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasuda
  • Patent number: 10014254
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 3, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani