Patents by Inventor Taiji Ema

Taiji Ema has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140235022
    Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 21, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Kazushi Fujita, Junji Oh
  • Patent number: 8778786
    Abstract: Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: July 15, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lance Scudder, Pushkar Ranade, Dalong Zhao, Teymur Bakhishev, Urupattur C. Sridharan, Taiji Ema, Toshifumi Mori, Mitsuaki Hori, Junji Oh, Kazushi Fujita, Yasunobu Torii
  • Patent number: 8766369
    Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazushi Fujita, Junji Oh
  • Publication number: 20140179072
    Abstract: The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 26, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazushi FUJITA, Taiji EMA, Hiroyuki OGAWA
  • Patent number: 8742547
    Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazutaka Yoshizawa, Taiji Ema
  • Patent number: 8741727
    Abstract: A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Junichi Ariyoshi, Taiji Ema, Toru Anezaki
  • Patent number: 8704311
    Abstract: The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazushi Fujita, Taiji Ema, Hiroyuki Ogawa
  • Patent number: 8698253
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: April 15, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Publication number: 20140091397
    Abstract: It is therefore an object of the present invention to provide a method in which, in a semiconductor integrated circuit device, a plurality of transistors having wide-rangingly different Ioff levels are embedded together in a semiconductor device including transistors each using a non-doped channel. By controlling an effective channel length, a leakage current is controlled without changing an impurity concentration distribution in a transistor including a non-doped channel layer and a screen layer provided immediately under the non-doped channel layer.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 3, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Kazushi Fujita, Yasunobu Torii, Mitsuaki Hori
  • Patent number: 8674421
    Abstract: The semiconductor device includes a first conductor formed over a semiconductor substrate; a first insulator formed over the first conductor; a second insulator formed over the first insulator, the second insulator having an etching characteristic different from an etching characteristic of the first insulator; a second conductor formed on the second insulator, the second conductor being in contact with the second insulator; a third insulator formed over the second conductor, the third insulator having an etching characteristic different from the etching characteristic of the second insulator; a first contact hole formed through the third insulator and the second conductor, the first contact hole reaching the second insulator; a third conductor formed in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; a second contact hole formed through the third insulator and the first insulator, the second contact hole reaching the first c
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Tohru Anezaki
  • Publication number: 20140035046
    Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.
    Type: Application
    Filed: July 3, 2013
    Publication date: February 6, 2014
    Inventors: Kazushi FUJITA, Taiji EMA, Mitsuaki HORI, Yasunobu TORII
  • Publication number: 20130299892
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Publication number: 20130302967
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Patent number: 8530308
    Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: September 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 8497176
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Patent number: 8426267
    Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: April 23, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 8415215
    Abstract: A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: April 9, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Junichi Ariyoshi, Taiji Ema
  • Patent number: 8404554
    Abstract: The method of manufacturing a semiconductor device includes a first conductor over a semiconductor substrate; forming a first insulator over the first conductor; forming a second insulator, having an etching characteristic different from an etching characteristic of the first insulator, over the first insulator; forming a second conductor on the second insulator, the second conductor being in contact with the second insulator; forming a third insulator, having an etching characteristic different from the etching characteristic of the second insulator, over the second conductor; forming a first contact hole though the third insulator and the second conductor, the first contact hole exposing the second insulator; forming a second contact hole through the third insulator and the first insulator, the second contact hole exposing the first conductor; forming a third conductor in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; form
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: March 26, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Tohru Anezaki
  • Publication number: 20130069206
    Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 21, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazutaka Yoshizawa, Taiji Ema, Takuya Moriki
  • Patent number: 8377807
    Abstract: Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: February 19, 2013
    Assignee: Suvolta, Inc.
    Inventors: Lucian Shifren, Taiji Ema