Patents by Inventor Taiji Sakai

Taiji Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170284748
    Abstract: Corrugated fins that have high heat transfer performance and do not cause clogging even in a gaseous environment in which particulate matter such as dust is present have wall surfaces on which are formed alternating parallel ridges and furrows with an angle of inclination of 10-60°. Defining Wh as the height of the ridges and furrows, Wp as the period of the ridges and furrows, Pf as the period of the corrugated fins, and Tf as the thickness of the plate forming the fins, the following conditions hold. Wh?0.3674·Wp+1.893·Tf?0.1584, 0.088<(Wh?Tf)/Pf<0.342, and a·Wp2+b·Wp+c<Wh, where a=0.004·Pf2?0.0696·Pf+0.3642 b=?0.0036·Pf2+0.0625·Pf?0.5752, and c=0.0007·Pf2+0.1041·Pf+0.2333.
    Type: Application
    Filed: September 15, 2015
    Publication date: October 5, 2017
    Inventors: Takuya BUNGO, Noriyuki ISHII, Atsushi OKUBO, Taiji SAKAI
  • Publication number: 20170153068
    Abstract: A corrugated fin heat exchanger is provided in which the direction in which louvers are cut and raised is inclined in one direction only, and in which heat transfer performance is improved above that of conventional fins. To accomplish this, the relationship H>Qup/(Qup?1)×?H is satisfied. H represents the core height of the heat exchanger, Qup represents the ratio of the amount of heat exchanged per corrugation between one-directional louver fins and multi-directional louver fins in an airflow part, and ?H represents the amount of increase in a heat transfer reduction region of a heat exchanger core as a result of changing from multi-directional louver fins to one-directional louver fins.
    Type: Application
    Filed: May 25, 2015
    Publication date: June 1, 2017
    Applicant: T.RAD Co., Ltd.
    Inventors: Takuya BUNGO, Atsushi OKUBO, Taiji SAKAI, Hirotaka UEKI, Kazuo MAEGAWA
  • Publication number: 20170125359
    Abstract: An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.
    Type: Application
    Filed: October 20, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Taiji Sakai, Seiki Sakuyama, Nobuhiro Imaizumi, Aki Dote
  • Publication number: 20170016684
    Abstract: In order to improve sealing performance when the open end of a tank is swaged and thereby secured inside an annular groove the surface of which is formed in a substantially rectangular shape with a seal material between the groove an the tank, flange parts protrude in a fan shape at the four corners of the seal material, and those flange parts are pressed by the corner sections of the annular groove, thereby preventing the seal material from moving in the corner sections.
    Type: Application
    Filed: February 26, 2015
    Publication date: January 19, 2017
    Inventors: Atsushi OKUBO, Taiji SAKAI, Takuya BUNGO
  • Publication number: 20160370127
    Abstract: In order to prevent deformation of a side member due to thermal stress in a heat exchanger in which water for cooling a high-temperature body circulates, a side member is formed in the shape of a groove, the cross section of which has side wall parts and a base part along the entire length in the lengthwise direction of a main body part, and both ends of the side member in the lengthwise direction are provided with a stepped part, which is formed as a step toward the outside of a core, and one or more brace-like ribs, which integrally connect the tip end and the base part of the stepped part in a slanting manner.
    Type: Application
    Filed: February 12, 2015
    Publication date: December 22, 2016
    Inventors: Atsushi OKUBO, Takuya BUNGO, Taiji SAKAI
  • Patent number: 9402313
    Abstract: A conductive material includes a first metal part whose main ingredient is a first metal; a second metal part formed on the first metal part and whose main ingredient is a second metal, the second metal having a melting point lower than a melting point of the first metal, which second metal can form a metallic compound with the first metal; and a third metal part whose main ingredient is a third metal, which third metal can make a eutectic reaction with the second metal.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: July 26, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Seiki Sakuyama, Taiji Sakai
  • Publication number: 20150132865
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Yoshiharu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Patent number: 8962470
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Patent number: 8922027
    Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: December 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Taiji Sakai, Nobuhiro Imaizumi
  • Publication number: 20140342504
    Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.
    Type: Application
    Filed: August 6, 2014
    Publication date: November 20, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Taiji SAKAI, Nobuhiro IMAIZUMI
  • Patent number: 8860232
    Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventors: Taiji Sakai, Nobuhiro Imaizumi
  • Publication number: 20140202739
    Abstract: A printed wiring board includes a Cu wiring pattern formed on a substrate. A first metal layer is formed on the Cu wiring pattern. A second metal layer is formed on the first metal layer. The first metal layer has a less reactivity with Cu than the second metal layer. The first metal layer and the second metal layer together cause an eutectic reaction.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Taiji Sakai, Seiki Sakuyama
  • Publication number: 20140140030
    Abstract: A conductive material includes a first metal part whose main ingredient is a first metal; a second metal part formed on the first metal part and whose main ingredient is a second metal, the second metal having a melting point lower than a melting point of the first metal, which second metal can form a metallic compound with the first metal; and a third metal part whose main ingredient is a third metal, which third metal can make a eutectic reaction with the second metal.
    Type: Application
    Filed: January 24, 2014
    Publication date: May 22, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Seiki Sakuyama, Taiji Sakai
  • Patent number: 8713792
    Abstract: A printed wiring board includes a Cu wiring pattern formed on a substrate. A first metal layer is formed on the Cu wiring pattern. A second metal layer is formed on the first metal layer. The first metal layer has a less reactivity with Cu than the second metal layer. The first metal layer and the second metal layer together cause an eutectic reaction.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventors: Taiji Sakai, Seiki Sakuyama
  • Patent number: 8673050
    Abstract: A conductive material includes a first metal part whose main ingredient is a first metal; a second metal part formed on the first metal part and whose main ingredient is a second metal, the second metal having a melting point lower than a melting point of the first metal, which second metal can form a metallic compound with the first metal; and a third metal part whose main ingredient is a third metal, which third metal can make a eutectic reaction with the second metal.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Seiki Sakuyama, Taiji Sakai
  • Patent number: 8479386
    Abstract: A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 9, 2013
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
  • Patent number: 8409931
    Abstract: A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Limited
    Inventors: Taiji Sakai, Nobuhiro Imaizumi, Masataka Mizukoshi
  • Publication number: 20120244665
    Abstract: A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion.
    Type: Application
    Filed: February 24, 2012
    Publication date: September 27, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Taiji SAKAI, Nobuhiro Imaizumi, Masataka Mizukoshi
  • Publication number: 20120217626
    Abstract: A method for manufacturing a semiconductor device, includes: placing a seal layer including a connection conductive film on the surface so that the connection conductive film is in contact with an electrode of a semiconductor element and a lead; electrically coupling the electrode and the lead through the connection conductive film; and sealing the semiconductor element by the seal layer.
    Type: Application
    Filed: January 19, 2012
    Publication date: August 30, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Taiji SAKAI, Kazukiyo Joshin, Tadahiro Imada, Nobuhiro Imaizumi, Keishiro Okamoto
  • Publication number: 20110056068
    Abstract: The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.
    Type: Application
    Filed: November 12, 2010
    Publication date: March 10, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi