Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.

Abstract: Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer.

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.

Abstract: Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer.

Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.

Abstract: Methods of fabricating solar cells, and the resulting solar cells, are described herein. In an example, a method of fabricating a solar cell includes forming a thin dielectric layer on a surface of a substrate by radical oxidation or plasma oxidation of the surface of the substrate. The method also involves forming a silicon layer over the thin dielectric layer. The method also involves forming a plurality of emitter regions from the silicon layer.

Abstract: Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer.

Abstract: Sputter tools are described. In one embodiment, an apparatus to support a wafer includes a pallet having a depression to receive the wafer. The pallet includes an opening below the depression, and an edge in the depression is to support the wafer over the opening. A cover at least partially covers the opening. In one example, the cover may be a plate with one or more holes, and a pipe may be located below each of the holes in the cover. In one embodiment, a wafer-processing system includes a processing chamber and a pallet with a depression to receive a wafer. The pallet has an opening below the depression, and an edge in the depression supports the wafer over the opening. In one such embodiment, a cover at least partially covers the opening. According to one embodiment, an energy-absorbing material is disposed below the opening in the pallet.

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Abstract: A process for radical assisted film deposition simultaneously on multiple wafer substrates is provided. The multiple wafer substrates are loaded into a reactor that is heated to a desired film deposition temperature. A stable species source of oxide or nitride counter ion is introduced into the reactor. An in situ radical generating reactant is also introduced into the reactor along with a cationic ion deposition source. The cationic ion deposition source is introduced for a time sufficient to deposit a cationic ion-oxide or a cationic ion-nitride film simultaneously on multiple wafer substrates. Deposition temperature is below a conventional chemical vapor deposition temperature absent the in situ radical generating reactant.

Abstract: A batch of wafer substrates is provided with each wafer substrate having a surface. Each surface is coated with a layer of material applied simultaneously to the surface of each of the batch of wafer substrates. The layer of material is applied to a thickness that varies less than four thickness percent across the surface and exclusive of an edge boundary and having a wafer-to-wafer thickness variation of less than three percent. The layer of material so applied is a silicon oxide, silicon nitride or silicon oxynitride with the layer of material being devoid of carbon and chlorine. Formation of silicon oxide or a silicon oxynitride requires the inclusion of a co-reactant. Silicon nitride is also formed with the inclusion of a nitrification co-reactant.

Abstract: An apparatus for heat treatment of a wafer is disclosed. The apparatus includes a heating chamber having a heat source. A cooling chamber is positioned adjacent to the heating chamber and includes a cooling source. A wafer holder is configured to move between the cooling chamber and the heating chamber through a passageway and one or more shutters defines the size of the passageway. The one or more shutters are movable between an open position where the wafer holder can pass through the passageway and an obstructing position which defines a passageway which is smaller than the passageway defined when the shutter is in the open position.

Abstract: An apparatus for heat treatment of a wafer. The apparatus includes a heating chamber having a heat source. A cooling chamber is positioned adjacent to the heating chamber and includes a cooling source. A wafer holder is configured to move between the cooling chamber and the heating chamber through a passageway and one or more shutters defines the size of the passageway. The one or more shutters are movable between an open position where the wafer holder can pass through the passageway and an obstructing position which defines a passageway which is smaller than the passageway defined when the shutter is in the open position.

Abstract: An apparatus for heat treatment of a wafer is disclosed. The apparatus includes a heating chamber having a heat source. A cooling chamber is positioned adjacent to the heating chamber and includes a cooling source. A wafer holder is configured to move between the cooling chamber and the heating chamber through a passageway and one or more shutters defines the size of the passageway. The one or more shutters are movable between an open position where the wafer holder can pass through the passageway and an obstructing position which defines a passageway which is smaller than the passageway defined when the shutter is in the open position.

Abstract: An apparatus for heat treatment of a wafer is disclosed. The apparatus includes a heating chamber having a heat source. A cooling chamber is positioned adjacent to the heating chamber and includes a cooling source. A wafer holder is configured to move between the cooling chamber and the heating chamber through a passageway and one or more shutters defines the size of the passageway. The one or more shutters are movable between an open position where the wafer holder can pass through the passageway and an obstructing position which defines a passageway which is smaller than the passageway defined when the shutter is in the open position.

Abstract: An apparatus for heat treatment of a wafer is disclosed. The apparatus includes a heating chamber having a heat source. A cooling chamber is positioned adjacent to the heating chamber and includes a cooling source. A wafer holder is configured to move between the cooling chamber and the heating chamber through a passageway and one or more shutters defines the size of the passageway. The one or more shutters are movable between an open position where the wafer holder can pass through the passageway and an obstructing position which defines a passageway which is smaller than the passageway defined when the shutter is in the open position.