Patents by Inventor Tak H. Ning

Tak H. Ning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200006366
    Abstract: Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.
    Type: Application
    Filed: April 4, 2019
    Publication date: January 2, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Jeng-Bang Yau, Tak H. Ning
  • Publication number: 20190363184
    Abstract: A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Inventors: Alexander Reznicek, Tak H. Ning, Jeng-Bang Yau, Bahman Hekmatshoartabari
  • Publication number: 20190355830
    Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 21, 2019
    Inventors: Karthik Balakrishnan, Jeng-Bang Yau, Alexander Reznicek, Tak H. Ning
  • Patent number: 10468503
    Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Jeng-Bang Yau, Alexander Reznicek, Tak H. Ning
  • Publication number: 20190326397
    Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Kevin K. Chan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Publication number: 20190312125
    Abstract: A bipolar junction transistor (BJT) containing sensor that includes a vertically orientated stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region in contact with a first sidewall of a vertically orientated base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region in contact with a second sidewall of the base region. The second extrinsic base region including a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 10, 2019
    Inventors: Alexander Reznicek, Tak H. Ning, Sufi Zafar, Oscar van der Straten
  • Publication number: 20190312126
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Publication number: 20190304968
    Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10424650
    Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.
    Type: Grant
    Filed: June 16, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10411109
    Abstract: A bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region is in contact with a first sidewall of a vertically oriented base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region is in contact with a second sidewall of the base region. The second extrinsic base region includes a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Tak H. Ning, Sufi Zafar, Oscar van der Straten
  • Patent number: 10396154
    Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Publication number: 20190257843
    Abstract: A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Bobby E. Feller, Jianqiang Lin, Robert D. Miller, Ramachandran Muralidhar, Tak H. Ning, Sufi Zafar
  • Publication number: 20190257844
    Abstract: A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Bobby E. Feller, Jianqiang Lin, Robert D. Miller, Ramachandran Muralidhar, Tak H. Ning, Sufi Zafar
  • Patent number: 10388648
    Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Publication number: 20190214398
    Abstract: A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10345317
    Abstract: A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bobby E. Feller, Jianqiang Lin, Robert D. Miller, Ramachandran Muralidhar, Tak H. Ning, Sufi Zafar
  • Publication number: 20190207011
    Abstract: A bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region is in contact with a first sidewall of a vertically oriented base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region is in contact with a second sidewall of the base region. The second extrinsic base region includes a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.
    Type: Application
    Filed: January 2, 2018
    Publication date: July 4, 2019
    Inventors: Alexander Reznicek, Tak H. Ning, Sufi Zafar, Oscar van der Straten
  • Publication number: 20190206859
    Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10332972
    Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Publication number: 20190189745
    Abstract: A method of forming an electrical device is provided that includes a semiconductor device and a passive resistor both integrated in a same vertically orientated epitaxially grown semiconductor material. The vertically orientated epitaxially grown semiconductor material is formed from a semiconductor surface of a supporting substrate. The vertically orientated epitaxially grown semiconductor material includes a resistive portion and a semiconductor portion, in which the sidewalls of the resistive portion are aligned with the sidewalls of the semiconductor portion. A semiconductor device is formed on the semiconductor portion of the vertically orientated epitaxially grown semiconductor material. A passive resistor is present in the resistive portion of the vertically orientated epitaxially grown semiconductor material, the resistive portion having a higher resistance than the semiconductor portion.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Tak H. Ning, Alexander Reznicek