Abstract: A bipolar junction transistor (BJT) containing sensor that includes a vertically orientated stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region in contact with a first sidewall of a vertically orientated base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region in contact with a second sidewall of the base region. The second extrinsic base region including a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.

Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.

Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.

Abstract: A bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region is in contact with a first sidewall of a vertically oriented base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region is in contact with a second sidewall of the base region. The second extrinsic base region includes a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.

Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

Abstract: A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.

Abstract: A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.

Abstract: A method of forming a pair of edge-emitting lasers is provided. The method includes forming a mesa from a substrate, forming a cover layer on the substrate around the mesa, and forming a first barrier layer on each of opposite sidewalls of the mesa. The method further includes forming a quantum well layer on each of the barrier layers, forming a second barrier layer on each of the quantum well layers, and forming a cladding layer on each of the second barrier layers.

Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.

Abstract: A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.

Abstract: A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.

Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.

Abstract: A bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region is in contact with a first sidewall of a vertically oriented base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region is in contact with a second sidewall of the base region. The second extrinsic base region includes a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.

Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.

Abstract: A method of forming an electrical device is provided that includes a semiconductor device and a passive resistor both integrated in a same vertically orientated epitaxially grown semiconductor material. The vertically orientated epitaxially grown semiconductor material is formed from a semiconductor surface of a supporting substrate. The vertically orientated epitaxially grown semiconductor material includes a resistive portion and a semiconductor portion, in which the sidewalls of the resistive portion are aligned with the sidewalls of the semiconductor portion. A semiconductor device is formed on the semiconductor portion of the vertically orientated epitaxially grown semiconductor material. A passive resistor is present in the resistive portion of the vertically orientated epitaxially grown semiconductor material, the resistive portion having a higher resistance than the semiconductor portion.

Abstract: A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.

Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.

Abstract: A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.

Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.

Abstract: A method of forming a pair of edge-emitting lasers is provided. The method includes forming a mesa from a substrate, forming a cover layer on the substrate around the mesa, and forming a first barrier layer on each of opposite sidewalls of the mesa. The method further includes forming a quantum well layer on each of the barrier layers, forming a second barrier layer on each of the quantum well layers, and forming a cladding layer on each of the second barrier layers.