Patents by Inventor Tak H. Ning

Tak H. Ning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bipolar transistor with carbon alloyed contacts
    Patent number: 9306042
    Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning
  • Optoelectronic devices with back contact
    Patent number: 9305964
    Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • LATERAL BIPOLAR TRANSISTOR WITH BASE EXTENSION REGION
    Publication number: 20160087068
    Abstract: A method of forming a base extension region for a lateral bipolar transistor. The base extension region may include forming an extrinsic base on an intrinsic base layer, the intrinsic base layer is on an insulator layer, a top portion of the intrinsic base layer is exposed on opposite sides of the extrinsic base; forming a base extension region by recessing the exposed top portion of the intrinsic base layer to a recessed surface, the recessed surface is above a top surface of the insulator layer, the base extension region is a region of the intrinsic base layer remaining above the recessed surface; and forming an emitter/collector in the intrinsic base layer, an intrinsic base is a portion of the intrinsic base layer between the emitter/collector, the emitter/collector is a distance from the extrinsic base of no less than a thickness of the base extension region.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Inventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau, Joonah Yoon
  • Bipolar junction transistor having multi-sided base contact
    Patent number: 9293454
    Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: March 22, 2016
    Assignee: Globalfoundries Inc.
    Inventors: Jin Cai, Tak H. Ning
  • Integrated finFET-BJT replacement metal gate
    Patent number: 9263583
    Abstract: A method of forming a semiconductor structure that includes forming a first recess and a second recess between a first pair of sidewall spacers and a second pair of sidewall spacers respectively, the first and second pair of sidewall spacers surrounding a fin on top of a buried dielectric layer, the fin is formed from a top most semiconductor layer of a semiconductor-on-insulator substrate. A high-k dielectric layer is deposited within the first and second recesses and a dummy titanium nitride layer is deposited on the high-k dielectric layer. The high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess and a silicon cap layer is deposited within the first and second recesses. Next, dopants are implanted into the silicon cap layer in the second recess without implanting dopants into the silicon cap layer in the first recess to form a BJT device.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jin Cai, Effendi Leobandung, Tak H. Ning
  • Symmetrical bipolar junction transistor array
    Patent number: 9263336
    Abstract: A method of manufacturing a bipolar junction transistor (BJT) array may include forming a substrate of doped silicon and forming a plurality of BJTs on the substrate. Each of the BJTs may have a first region and a second region sandwiching a base region vertically. The first region may be in contact with the substrate, where the BJTs are formed in a first row and a second row. The first row and the second row may each have BJTs separated from one another by a word line distance and the first row and second row may be separated by a bit line distance. A plurality of word line contacts may be formed laterally enclosing and electrically connected to each base region of the BJTs. The word line contacts may have a lateral thickness more than one half the word line distance and less than one half the bit line distance.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Jin Cai, SangBum Kim, Chung H. Lam, Tak H. Ning
  • Junction field effect transistor with an epitaxially grown gate structure
    Patent number: 9240497
    Abstract: A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: January 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tak H. Ning, Kangguo Cheng, Ali Khakifirooz, Pranita Kerber
  • BIOSENSORS INCLUDING SURFACE RESONANCE SPECTROSCOPY AND SEMICONDUCTOR DEVICES
    Publication number: 20160011216
    Abstract: A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 14, 2016
    Inventors: Bobby E. Feller, Jianqiang Lin, Robert D. Miller, Ramachandran Muralidhar, Tak H. Ning, Sufi Zafar
  • Heterogeneous integration of group III nitride on silicon for advanced integrated circuits
    Patent number: 9236251
    Abstract: Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Can Bayram, Cheng-Wei Cheng, Tak H. Ning, Devendra K. Sadana, Kuen-Ting Shiu
  • HYBRID BIPOLAR JUNCTION TRANSISTOR
    Publication number: 20150357386
    Abstract: Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 10, 2015
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Tak H. Ning, Davood Shahrjerdi
  • Back-end transistors with highly doped low-temperature contacts
    Patent number: 9209024
    Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wilfried E. Haensch, Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Tak H. Ning, Ghavam G. Shahidi, Davood Shahrjerdi
  • SYMMETRICAL BIPOLAR JUNCTION TRANSISTOR ARRAY
    Publication number: 20150348844
    Abstract: A method of manufacturing a bipolar junction transistor (BJT) array may include forming a substrate of doped silicon and forming a plurality of BJTs on the substrate. Each of the BJTs may have a first region and a second region sandwiching a base region vertically. The first region may be in contact with the substrate, where the BJTs are formed in a first row and a second row. The first row and the second row may each have BJTs separated from one another by a word line distance and the first row and second row may be separated by a bit line distance. A plurality of word line contacts may be formed laterally enclosing and electrically connected to each base region of the BJTs. The word line contacts may have a lateral thickness more than one half the word line distance and less than one half the bit line distance.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Jin Cai, SangBum Kim, Chung H. Lam, Tak H. Ning
  • Charge sensors using inverted lateral bipolar junction transistors
    Patent number: 9170338
    Abstract: A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Jin Cai, Tak H. Ning, Jeng-Bang Yau, Sufi Zafar
  • SOI bipolar junction transistor with substrate bias voltages
    Patent number: 9171924
    Abstract: A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: October 27, 2015
    Assignee: GlobalFoundries U.S. 2 LLC
    Inventors: Jin Cai, Tak H. Ning
  • CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS
    Publication number: 20150295119
    Abstract: A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.
    Type: Application
    Filed: April 15, 2015
    Publication date: October 15, 2015
    Inventors: Jin Cai, Tak H. Ning, Jeng-Bang Yau, Sufi Zafar
  • Hybrid bipolar junction transistor
    Patent number: 9147715
    Abstract: Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: September 29, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Tak H. Ning, Davood Shahrjerdi
  • ACTIVE MATRIX USING HYBRID INTEGRATED CIRCUIT AND BIPOLAR TRANSISTOR
    Publication number: 20150270326
    Abstract: A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.
    Type: Application
    Filed: May 20, 2015
    Publication date: September 24, 2015
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Ghavam G. Shahidi, Davood Shahrjerdi
  • HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
    Publication number: 20150263143
    Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.
    Type: Application
    Filed: May 29, 2015
    Publication date: September 17, 2015
    Inventors: Bahman Hekmatshoar-Tabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
    Publication number: 20150263129
    Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.
    Type: Application
    Filed: May 29, 2015
    Publication date: September 17, 2015
    Inventors: Bahman Hekmatshoar-Tabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • APPLICATION OF SUPER LATTICE FILMS ON INSULATOR TO LATERAL BIPOLAR TRANSISTORS
    Publication number: 20150263095
    Abstract: A lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning