Abstract: A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

Abstract: A complementary bipolar junction transistor (BJT) integrated structure and methods for fabricating and operating such. The structure includes a monolithic substrate and conductive first and second backplates electrically isolated from each other. An NPN lateral BJT is superposed over the first backplate, and a PNP lateral BJT is superposed over the second backplate. A buried oxide (BOX) layer is positioned between the NPN lateral BJT and the first backplate, and between the PNP lateral BJT and the second backplate.

Abstract: An integrated sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second bipolar junction transistors (BJTs). The first BJT has a base that is electrically coupled with the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second BJTs and the sensing structure are monolithically formed a common substrate.

Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.

Abstract: A lateral bipolar junction transistor (BJT) magnetic field sensor that includes a layout of two or more adjacent lateral BJT devices. Each BJT includes a semiconductor base region of a first conductivity type doping, a semiconductor emitter region of a second conductivity type doping and laterally contacting the base region; and a first semiconductor collector region of a second conductivity type doping contacting said base region on an opposite side thereof. A second collector region of the second conductivity type doping is also formed contacting the base region on the opposite side thereof in spaced apart relation with the first collector region. The first adjacent lateral BJT device includes the emitter, base and first collector region and the second adjacent lateral BJT device includes the emitter, base and second collector region. The sensor induces a detectable difference in collector current amounts in the presence of an external magnetic field transverse to a plane defined by the layout.

Abstract: Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.

Abstract: A complementary lateral bipolar SRAM device and method of operating. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage.

Abstract: Lateral SOI bipolar transistor structures are provided including an intrinsic base semiconductor material portion in which all surfaces of the intrinsic base not forming an interface with either a collector semiconductor material portion or an emitter semiconductor material portion, contain an extrinsic base semiconductor material portion. Each extrinsic base semiconductor material portion is of the same conductivity type as that of the intrinsic base semiconductor material portion, yet each extrinsic base semiconductor material portion has a higher dopant concentration than the intrinsic base semiconductor material portion. The intrinsic base semiconductor material portion of the lateral SOI bipolar transistors of the present application does not have any interface with surrounding insulator material layers. As such, any potential charge build-up in the surrounding insulator material layers is shielded by the extrinsic base semiconductor material portions.

Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.

Abstract: A lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.

Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

Abstract: A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.

Abstract: A static random access memory (SRAM) cell is provided. The SRAM cell consists of two cross coupled integrated-injection logic (I2L) inverter devices. Each inverter device contains two lateral bipolar transistors (e.g., NPN- and PNP-type lateral bipolar transistors). Each of the inverter devices, and hence each lateral bipolar transistor, is formed on a surface of an insulator layer of a semiconductor-on-insulator (SOI) substrate.

Abstract: A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.

Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.

Abstract: A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.

Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.