Abstract: A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A method for fabricating a photovoltaic device includes forming a first contact on a crystalline substrate, by epitaxially growing a first doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller, and a thickness configured to reduce Auger recombination in the epitaxially grown doped layer. A first passivation layer is formed on the first doped layer. A second contact is formed on the crystalline substrate on a side opposite the first contact by epitaxially growing a second doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller and a thickness configured to reduce Auger recombination in the second epitaxially grown doped layer. A second passivation layer is formed on the second doped layer.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: High speed bipolar junction transistor switches for high voltage operations. An example switch includes a bipolar junction transistor including a collector region positioned over a buried insulator region. The collector region includes dopants of a first conductivity type. A field effect transistor includes a source region also positioned over a buried insulator region. The source region electrically is coupled to the collector region such that all current passing the collector region enters the source region.

Abstract: Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

Abstract: Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.

Abstract: Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.

Abstract: A method for fabricating a photovoltaic device includes forming a first contact on a crystalline substrate, by epitaxially growing a first doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller, and a thickness configured to reduce Auger recombination in the epitaxially grown doped layer. A first passivation layer is formed on the first doped layer. A second contact is formed on the crystalline substrate on a side opposite the first contact by epitaxially growing a second doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller and a thickness configured to reduce Auger recombination in the second epitaxially grown doped layer. A second passivation layer is formed on the second doped layer.

Abstract: A method for fabricating a photovoltaic device includes forming a first contact on a crystalline substrate, by epitaxially growing a first doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller, and a thickness configured to reduce Auger recombination in the epitaxially grown doped layer. A first passivation layer is formed on the first doped layer. A second contact is formed on the crystalline substrate on a side opposite the first contact by epitaxially growing a second doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller and a thickness configured to reduce Auger recombination in the second epitaxially grown doped layer. A second passivation layer is formed on the second doped layer.

Abstract: Lateral SOI bipolar transistor structures are provided including an intrinsic base semiconductor material portion in which all surfaces of the intrinsic base not forming an interface with either a collector semiconductor material portion or an emitter semiconductor material portion, contain an extrinsic base semiconductor material portion. Each extrinsic base semiconductor material portion is of the same conductivity type as that of the intrinsic base semiconductor material portion, yet each extrinsic base semiconductor material portion has a higher dopant concentration than the intrinsic base semiconductor material portion. The intrinsic base semiconductor material portion of the lateral SOI bipolar transistors of the present application does not have any interface with surrounding insulator material layers. As such, any potential charge build-up in the surrounding insulator material layers is shielded by the extrinsic base semiconductor material portions.

Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.

Abstract: A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric.

Abstract: A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode.

Abstract: A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region.

Abstract: A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.