Patents by Inventor Takaaki Hagiwara
Takaaki Hagiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120251391Abstract: An automatic analyzer comprises selection means for selecting whether a preparatory operation, specified from a plurality of analysis preparation processes of the automatic analyzer, should be executed in an initial process at the powering on of the analyzer or after the start of the actual analysis (i.e., in parallel with the sample analysis operation). For example, the automatic analyzer is equipped with means which allows the analyzer to execute a “system liquid replacement operation”, a “sample nozzle pressure sensor checking operation”, a “reaction vessel discarding operation” and a “pre-cleaning liquid replacement operation” which among various operations that are executed in the preparation process in conventional immunological analyzing apparatus in processes other than the preparation process.Type: ApplicationFiled: December 20, 2010Publication date: October 4, 2012Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Takaaki Hagiwara, Yoshiyuki Tanaka, Kazunori Yamazawa
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Patent number: 5604142Abstract: This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.Type: GrantFiled: April 10, 1995Date of Patent: February 18, 1997Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
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Patent number: 5519244Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: July 6, 1994Date of Patent: May 21, 1996Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5472891Abstract: This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.Type: GrantFiled: June 14, 1994Date of Patent: December 5, 1995Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukuda, Hideaki Yamamoto
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Patent number: 5348898Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: January 26, 1993Date of Patent: September 20, 1994Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5340760Abstract: This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.Type: GrantFiled: December 15, 1992Date of Patent: August 23, 1994Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
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Patent number: 5252505Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: January 15, 1992Date of Patent: October 12, 1993Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5189497Abstract: This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.Type: GrantFiled: September 24, 1991Date of Patent: February 23, 1993Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
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Patent number: 5114870Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: May 15, 1989Date of Patent: May 19, 1992Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5097446Abstract: A time circuit is provided for a nonvolatile memory device which can electrically be written into. When the write operation on a particular memory cell lasting a relatively long period of time is specified from an external device, the memory device stops the write operation on that memory cell, irrespective of the external write operaiton specification, when the time set on the timer circuit has elapsed. The nonvolatile memory device has memory cells, each consisting of a single transistor. The erase operation on the memory cells is controlled according to a current flowing through these memory cells.Type: GrantFiled: May 23, 1989Date of Patent: March 17, 1992Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuyoshi Shoji, Takaaki Hagiwara, Tadashi Muto, Shun-ichi Saeki, Yasurou Kubota, Kazuto Izawa, Yoshiaki Kamigaki, Shin-ichi Minami, Yuko Nabetani
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Patent number: 5079603Abstract: This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.Type: GrantFiled: April 30, 1990Date of Patent: January 7, 1992Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
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Patent number: 4972371Abstract: An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.Type: GrantFiled: June 7, 1988Date of Patent: November 20, 1990Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Takaaki Hagiwara, Satoshi Meguro, Toshiaki Nishimoto, Takeshi Wada, Kiyofumi Uchibori, Tadashi Muto, Hitoshi Kume, Hideaki Yamamoto, Tetsuo Adachi, Toshihisa Tsukada, Toshiko Koizumi
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Patent number: 4851364Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: April 10, 1986Date of Patent: July 25, 1989Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 4668970Abstract: In a semiconductor device which includes an insulation film through which a charge can tunnel, a gate insulation film of a material different from the material of said insulation film or having a thickness different from that of said insulation film, and a floating gate extending over said tunnelable insulation film, the improvement wherein at least two sides of said tunnelable region are bounded by a device separation oxide film.Type: GrantFiled: December 2, 1985Date of Patent: May 26, 1987Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Masatada Horiuchi, Shinichi Minami, Toru Kaga
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Patent number: 4656607Abstract: In a semiconductor memory made up of semiconductor memory elements, each consisting of a transistor of an MOS structure which has a charge-storage layer and which is formed on a semiconductor substrate, the improvement wherein a switching element is provided so that positive or negative charge can be stored or discharged from the charge-storage layer in a mode for writing data, and the charge-storage layer can be allowed to float electrically when in a mode for reading data.Type: GrantFiled: July 19, 1984Date of Patent: April 7, 1987Assignee: Hitachi, Ltd.Inventors: Takaaki Hagiwara, Toru Kaga, Hiroo Masuda
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Patent number: 4654828Abstract: A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal-silicon nitride-silicon dioxide-semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal-silicon dioxide-semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.Type: GrantFiled: October 15, 1985Date of Patent: March 31, 1987Assignee: Hitachi, Ltd.Inventors: Takaaki Hagiwara, Yokichi Itoh, Ryuji Kondo, Yuji Yatsuda, Shinichi Minami
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Patent number: 4633438Abstract: In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.A memory cell capable of extremely large scale integration can be obtained.Type: GrantFiled: December 13, 1984Date of Patent: December 30, 1986Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering Ltd.Inventors: Hitoshi Kume, Takaaki Hagiwara, Masatada Horiuchi, Toru Kaga, Yasuo Igura, Akihiro Shimizu
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Patent number: 4586238Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: April 21, 1983Date of Patent: May 6, 1986Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 4514830Abstract: An LSI memory comprises a memory array including usual memory cells arranged in a matrix form, usual address transistors for selecting usual lines connected to the columns or rows of the memory array, address lines for controlling the usual address transistors, spare memory cells provided in the memory array, a spare line connected to the spare memory cells, spare address transistors connected between the address lines and the spare lines, and nonvolatile memory elements connected between the sources of the spare address transistors and the ground. By putting any one of the nonvolatile memory elements into the written state, any one of the spare address transistors are conditioned into an active state so that the spare line can be substituted for a defective usual line.Type: GrantFiled: February 2, 1982Date of Patent: April 30, 1985Assignee: Hitachi, Ltd.Inventors: Takaaki Hagiwara, Masatada Horiuchi, Ryuji Kondo, Yuji Yatsuda, Shinichi Minami
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Patent number: 4460980Abstract: A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal--silicon nitride--silicon dioxide--semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal--silicon dioxide--semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.Type: GrantFiled: October 2, 1980Date of Patent: July 17, 1984Assignee: Hitachi, Ltd.Inventors: Takaaki Hagiwara, Yokichi Itoh, Ryuji Kondo, Yuji Yatsuda, Shinichi Minami