Patents by Inventor Takaaki Hagiwara

Takaaki Hagiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4443718
    Abstract: A nonvolatile semiconductor memory including a memory matrix having a plurality of memory cells with nonvolatile memory elements and arranged in the form of a matrix, a selecting circuit for selecting a desired memory cell from the memory matrix, and a read-out circuit for reading out the information stored in the selected memory cell. The read-out circuit includes a sense amplifier and an output buffer. The sensed amplifier includes an inverter having a load element to which a supply voltage is applied and a selected memory cell acting as a driver element. The output buffer includes a level shift circuit for shifting the level of an output signal voltage from the sense amplifier with the level shift circuit including a stabilizing circuit for stabilizing the level of the shifted signal voltage during fluctuations in the supply voltage. An output driver circuit is provided for receiving the shifted signal voltage from the level shift circuit.
    Type: Grant
    Filed: September 19, 1980
    Date of Patent: April 17, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Takaaki Hagiwara, Yuji Yatsuda
  • Patent number: 4308596
    Abstract: In a memory array of memory cells each having at least a gate, a substrate, a source and a drain, a writing operation is effected when the substrate and the source and drain are at the same potential and when a potential difference V.sub.p exists between the potential of the substrate and the source and drain and that at the gate. The stored contents are erased when a potential difference V.sub.p exists between the gate and the substrate. The stored condition is prevented from changing when a potential difference V.sub.p exists between the substrate and the gate and when a potential difference V.sub.wd exists between the substrate and the source and drain. When such a memory array is partially erased, cells not to be erased are sequentially driven by applying a voltage V.sub.wd between the source and drain and the substrate of the cell, applying a voltage V.sub.p between the gate and the substrate of the cell, and applying the same potential to the substrate and the gate of the cell.
    Type: Grant
    Filed: October 4, 1979
    Date of Patent: December 29, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Takai, Yuzo Kita, Yoshimune Hagiwara, Terumi Sawase, Takaaki Hagiwara
  • Patent number: 4264376
    Abstract: A metal-silicon nitride-silicon oxide-substrate (MNOS) type nonvolatile memory device is disclosed. After the silicon nitride film has been formed, the heat treatment in the hydrogen atmosphere is performed. As a result of this heat treatment, the degradation of the memory retention characteristic is prevented so that a nonvolatile memory device having a silicon gate can be obtained which is comparable to a conventional nonvolatile memory device having an aluminum gate.
    Type: Grant
    Filed: August 15, 1979
    Date of Patent: April 28, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Yatsuda, Shinichi Minami, Ryuji Kondo, Takaaki Hagiwara, Yokichi Itoh