Patents by Inventor Takafumi Kikuchi

Takafumi Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8952527
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8873202
    Abstract: A head gimbal assembly includes a base plate, a load beam, a first end of which is supported by the base plate, a magnetic head supported at a second end of the load beam, a flexure including a plurality of wirings electrically connected to the magnetic head, the flexure extending from a surface of the base plate to an edge of the base plate, an adhesive applied in a space formed between the surface of the base plate and a surface of the flexure facing the surface of the base plate to bond the flexure to the base plate and to the edge of the base plate.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Nesori, Yasutaka Sasaki, Takafumi Kikuchi
  • Publication number: 20140117541
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Application
    Filed: January 7, 2014
    Publication date: May 1, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Publication number: 20140118863
    Abstract: A head gimbal assembly includes a base plate, a load beam, a first end of which is supported by the base plate, a magnetic head supported at a second end of the load beam, a flexure including a plurality of wirings electrically connected to the magnetic head, the flexure extending from a surface of the base plate to an edge of the base plate, an adhesive applied in a space formed between the surface of the base plate and a surface of the flexure facing the surface of the base plate to bond the flexure to the base plate and to the edge of the base plate.
    Type: Application
    Filed: June 11, 2013
    Publication date: May 1, 2014
    Inventors: Hirofumi NESORI, Yasutaka SASAKI, Takafumi KIKUCHI
  • Publication number: 20140077391
    Abstract: A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.
    Type: Application
    Filed: September 14, 2013
    Publication date: March 20, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Takashi Kikuchi, Takafumi Kikuchi
  • Patent number: 8653655
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8605390
    Abstract: According to one embodiment, a head gimbal assembly includes a suspension, a head, and a conductor trace on the suspension, including one end portion electrically connected to the head and the other end portion includes a terminal area. The conductor trace includes a thin metal plate, a base insulating layer on the thin metal plate, a trace pattern on the base insulating layer, including a plurality of conductors and a plurality of first and second connection terminals continuous with the conductors, and a cover insulating layer on the base insulating layer, configured to cover the trace pattern. The terminal area includes an opening including two opposite side edges, the first connection terminals extend into the opening from one of the side edges thereof, and the second connection terminals extend into the opening from the other side edge thereof.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takafumi Kikuchi, Yasutaka Sasaki
  • Publication number: 20130320571
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Application
    Filed: August 6, 2013
    Publication date: December 5, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8524534
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8278147
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8254064
    Abstract: According to one embodiment, a head gimbal assembly includes a load beam, a metal plate mounted on the load beam and constituting a gimbal includes a limiter portion, a flexure includes a plurality of conductors formed over the metal plate with an insulating layer therebetween, a slider includes a head and mounted on the gimbal, and a positioning reference mark formed on the limiter portion by parts of the conductors and configured to position the slider. The plurality of conductors includes conductors which conduct to the positioning reference mark through the metal plate and constitute an interleaved structure.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takafumi Kikuchi
  • Publication number: 20120134047
    Abstract: According to one embodiment, a head gimbal assembly includes a suspension, a head, and a conductor trace on the suspension, including one end portion electrically connected to the head and the other end portion includes a terminal area. The conductor trace includes a thin metal plate, a base insulating layer on the thin metal plate, a trace pattern on the base insulating layer, including a plurality of conductors and a plurality of first and second connection terminals continuous with the conductors, and a cover insulating layer on the base insulating layer, configured to cover the trace pattern. The terminal area includes an opening including two opposite side edges, the first connection terminals extend into the opening from one of the side edges thereof, and the second connection terminals extend into the opening from the other side edge thereof.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 31, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takafumi KIKUCHI, Yasutaka SASAKI
  • Publication number: 20120002322
    Abstract: According to one embodiment, a head gimbal assembly includes a load beam, a metal plate mounted on the load beam and constituting a gimbal includes a limiter portion, a flexure includes a plurality of conductors formed over the metal plate with an insulating layer therebetween, a slider includes a head and mounted on the gimbal, and a positioning reference mark formed on the limiter portion by parts of the conductors and configured to position the slider. The plurality of conductors includes conductors which conduct to the positioning reference mark through the metal plate and constitute an interleaved structure.
    Type: Application
    Filed: June 3, 2011
    Publication date: January 5, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takafumi Kikuchi
  • Patent number: 8059369
    Abstract: According to one embodiment, a head gimbal assembly of a disk drive includes an arm and a suspension extending from the arm, a head supported by the suspension, and a flexure on the arm and the suspension. One end portion of the flexure is electrically connected to the head, and the other end portion thereof includes a terminal area. The flexure includes a base insulating layer, a conductor pattern formed on the base insulating layer and having a plurality of connection terminals, and a cover insulating layer formed on the base insulating layer so as to cover the conductor pattern. The connection terminals are exposed to the inside of an opening in the base and cover insulating layers with a protective insulating layer and a thin metal plate overlaid on one surface of each of the connection terminals.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: November 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takafumi Kikuchi, Yasutaka Sasaki
  • Publication number: 20110171780
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Application
    Filed: March 22, 2011
    Publication date: July 14, 2011
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Publication number: 20110133336
    Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.
    Type: Application
    Filed: February 17, 2011
    Publication date: June 9, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
  • Patent number: 7897509
    Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: March 1, 2011
    Assignee: Renesas Electronics Corp.
    Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
  • Patent number: 7859095
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: December 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Publication number: 20100296195
    Abstract: According to one embodiment, a head gimbal assembly of a disk drive includes an arm and a suspension extending from the arm, a head supported by the suspension, and a flexure on the arm and the suspension. One end portion of the flexure is electrically connected to the head, and the other end portion thereof includes a terminal area. The flexure includes a base insulating layer, a conductor pattern formed on the base insulating layer and having a plurality of connection terminals, and a cover insulating layer formed on the base insulating layer so as to cover the conductor pattern. The connection terminals are exposed to the inside of an opening in the base and cover insulating layers with a protective insulating layer and a thin metal plate overlaid on one surface of each of the connection terminals.
    Type: Application
    Filed: January 25, 2010
    Publication date: November 25, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takafumi Kikuchi, Yasutaka Sasaki
  • Publication number: 20100258948
    Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 14, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa