Patents by Inventor Takaharu Yamano

Takaharu Yamano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10134680
    Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 20, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
  • Publication number: 20170365559
    Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.
    Type: Application
    Filed: August 14, 2017
    Publication date: December 21, 2017
    Inventors: Takaharu YAMANO, Hajime IIZUKA, Hideaki SAKAGUCHI, Toshio KOBAYASHI, Tadashi ARAI, Tsuyoshi KOBAYASHI, Tetsuya KOYAMA, Kiyoaki IIDA, Tomoaki MASHIMA, Koichi TANAKA, Yuji KUNIMOTO, Takashi YANAGISAWA
  • Patent number: 9768122
    Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: September 19, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
  • Patent number: 9564364
    Abstract: A semiconductor device includes a semiconductor substrate, which includes a through hole that extends through the semiconductor substrate. An insulative layer includes a first surface, an opposite second surface covering the semiconductor substrate, and an opening aligned with the through hole. An insulative film covers an inner wall surface of the semiconductor substrate and the opening. A through electrode is formed in the through hole and the opening inward from the insulative film. The through electrode includes a first end surface that forms a pad exposed from the first surface of the insulative layer. The first end surface of the through electrode is flush with the first surface of the insulative layer.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 7, 2017
    Assignee: Shinko Electric Industries Co., LTD.
    Inventor: Takaharu Yamano
  • Publication number: 20160358858
    Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: Takaharu YAMANO, Hajime IIZUKA, Hideaki SAKAGUCHI, Toshio KOBAYASHI, Tadashi ARAI, Tsuyoshi KOBAYASHI, Tetsuya KOYAMA, Kiyoaki IIDA, Tomoaki MASHIMA, Koichi TANAKA, Yuji KUNIMOTO, Takashi YANAGISAWA
  • Patent number: 9451702
    Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: September 20, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
  • Patent number: 9048225
    Abstract: A semiconductor device includes a semiconductor substrate. A through hole extends through the semiconductor substrate. A first insulating layer covers an upper surface of the semiconductor substrate and includes an opening in communication with the through hole. An insulating film covers wall surfaces of the through hole and the opening. A through electrode is formed in the through hole and the opening. A first connection terminal includes an electroless plating metal layer formed on an end surface of the through electrode and an end surface of the insulating film. The first connection terminal has a larger diameter than the through electrode. A wiring pattern is laminated on a lower surface of the semiconductor substrate. An electrode pad is connected to the wiring pattern. The through electrode is connected to the wiring pattern.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: June 2, 2015
    Assignee: Shinko Electric Industries Co., LTD.
    Inventors: Sumihiro Ichikawa, Takaharu Yamano
  • Publication number: 20140313681
    Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.
    Type: Application
    Filed: July 1, 2014
    Publication date: October 23, 2014
    Inventors: Takaharu YAMANO, Hajime IIZUKA, Hideaki SAKAGUCHI, Toshio KOBAYASHI, Tadashi ARAI, Tsuyoshi KOBAYASHI, Tetsuya KOYAMA, Kiyoaki IIDA, Tomoaki MASHIMA, Koichi TANAKA, Yuji KUNIMOTO, Takashi YANAGISAWA
  • Publication number: 20140239508
    Abstract: A semiconductor device includes a semiconductor substrate. A through hole extends through the semiconductor substrate. A first insulating layer covers an upper surface of the semiconductor substrate and includes an opening in communication with the through hole. An insulating film covers wall surfaces of the through hole and the opening. A through electrode is formed in the through hole and the opening. A first connection terminal includes an electroless plating metal layer formed on an end surface of the through electrode and an end surface of the insulating film. The first connection terminal has a larger diameter than the through electrode. A wiring pattern is laminated on a lower surface of the semiconductor substrate. An electrode pad is connected to the wiring pattern. The through electrode is connected to the wiring pattern.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: Shinko Electric Industries Co., LTD.
    Inventors: Sumihiro Ichikawa, Takaharu Yamano
  • Patent number: 8793868
    Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: August 5, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
  • Patent number: 8779573
    Abstract: Semiconductor chips are placed in recesses of a support carrier with electrode surfaces facing upward in a state where the semiconductor chips are arranged separately from each other. A seal resin part is formed by encapsulating the semiconductor chips by an insulating resin on said support carrier. Rewiring patterns are formed on a top surface of the seal resin part. External connection terminals are formed on the rewiring patterns. Bottom parts of the recesses of the support carrier are removed from the seal resin part while maintaining reinforcing members of the support carrier to be remained. The semiconductor packages are individualized by cutting the seal resin part along an outside of each reinforcing member.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: July 15, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Syota Miki, Takaharu Yamano
  • Patent number: 8564116
    Abstract: A semiconductor device includes a reinforcement plate having an accommodating hole and a through hole extending from a first surface to a second surface, a semiconductor chip including a chip core and a pad formed on a pad surface of the chip core, the semiconductor chip disposed in the accommodating hole with the pad surface flush with the first surface, the chip core having substantially the same thickness as the reinforcement plate and including a semiconductor substrate, a through-hole electrode disposed in the through hole, resin sealing the semiconductor chip and the reinforcement plate, a interconnection pattern disposed on the first-surface side of the reinforcement plate to connect between the through-hole electrode and the pad, and a interconnection pattern disposed on the second-surface side of the reinforcement plate to be connected to the through-hole electrode, wherein the reinforcement plate is made of the same material as the semiconductor substrate.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: October 22, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Patent number: 8415796
    Abstract: A semiconductor device includes a semiconductor substrate including a bump electrode, a first insulating layer formed on the semiconductor substrate and arranged to a lateral direction of the bump electrode, a first wiring layer formed on the first insulating layer and connected to the bump electrode, a second insulating layer formed on the first wiring layer, a via hole formed in the second insulating layer, and reaching the first wiring layer, a second wiring layer formed on the second insulating layer and connected to the first wiring layer via a via conductor formed in the via hole, and an external connection terminal connected to the second wiring layer, wherein an elastic modulus of the second insulating layer is set lower than an elastic modulus of the first insulating layer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 9, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Patent number: 8402644
    Abstract: A method of manufacturing an electronic parts packaging structure including the steps of preparing a plurality of sheet-like units each of which is constructed by a first insulating layer, a wiring formed on one surface of the first insulating layer, electronic parts connected to the wiring, a second insulating layer formed on an one surface side of the first insulating layer to cover the electronic parts, and a connecting portion for connecting electrically the wiring, and stacking mutually the units to arrange directions of unit adjacent in a thickness direction alternately oppositely, and bonding the units such that electronic parts of respective units are electrically connected mutually via connecting portions.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: March 26, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Toshio Gomyo, Yukiharu Takeuchi, Hidenori Takayanagi, Takaharu Yamano
  • Publication number: 20130037943
    Abstract: A semiconductor device includes a semiconductor substrate, which includes a through hole that extends through the semiconductor substrate. An insulative layer includes a first surface, an opposite second surface covering the semiconductor substrate, and an opening aligned with the through hole. An insulative film covers an inner wall surface of the semiconductor substrate and the opening. A through electrode is formed in the through hole and the opening inward from the insulative film. The through electrode includes a first end surface that forms a pad exposed from the first surface of the insulative layer. The first end surface of the through electrode is flush with the first surface of the insulative layer.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 14, 2013
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Patent number: 8349733
    Abstract: A manufacturing method of a substrate with through electrodes, comprising a substrate having through holes, and through electrodes received in the through holes, includes a through electrode formation step of forming the through electrodes on a support plate, a substrate formation step of forming the substrate, a through electrode reception step of stacking the substrate on the support plate 45 and receiving the through electrodes in the through holes, a resin filling step of filling gaps between side surfaces of the through electrodes and inner walls of the through holes of the substrate 11 with a resin, and a support plate removal step of removing the support plate after the resin filling step.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: January 8, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Patent number: 8299586
    Abstract: A disclosed semiconductor device includes a semiconductor chip having an electrode pad on a circuit forming face of the semiconductor chip, an internal connection terminal formed on the electrode pad, a stepped portion formed along an outer edge portion of the circuit forming face of the semiconductor chip, a first insulating layer formed on the circuit forming face of the semiconductor chip to cover at least the stepped portion, a second insulating layer formed on the circuit forming face of the semiconductor chip to cover the first insulating layer, and an interconnection formed on the second insulating layer and electrically connected to the electrode pad via the internal connection terminal.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: October 30, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takaharu Yamano, Syota Miki
  • Patent number: 8253229
    Abstract: In a stacked layer type semiconductor package constructed by stacking a plurality of packages with each other, the plurality of packages include a semiconductor package including: a semiconductor chip; a substrate in which a concave portion has been formed, the semiconductor chip being mounted in the concave portion; and a wiring line structure constructed in such a manner that the wiring line structure can be externally connected to the semiconductor chip at least just above and just under the semiconductor chip.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: August 28, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takaharu Yamano, Tsuyoshi Kobayashi
  • Patent number: 8232639
    Abstract: In a method of manufacturing a semiconductor-device mounted board, connection terminals are formed on electrode pads on a semiconductor integrated circuit respectively. A first insulating layer is formed to cover the connection terminals. A plate-like medium having a rough surface is disposed on the first insulating layer. The rough surface of the plate-like medium is pressed onto the first insulating layer so that a part of each of the connection terminals is exposed. A semiconductor device is produced by removing the plate-like medium. A second insulating layer is formed to cover side surfaces of the semiconductor device. A wiring pattern is formed to cover surfaces of the first and second insulating layers, the wiring pattern being electrically connected to the exposed connection terminal parts.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 31, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Toshio Kobayashi, Takaharu Yamano, Takashi Kurihara
  • Patent number: 8211754
    Abstract: A semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, in which a size reduction may be attempted. The device includes a semiconductor chip, an external connection terminal pad electrically connected to the semiconductor chip, and an encapsulation resin encapsulating the semiconductor chip, wherein a wiring pattern on which the external connection terminal pad is formed is provided between the semiconductor chip and the external connection terminal pad, and the semiconductor chip is flip-chip bonded to the wiring pattern.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: July 3, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano