Abstract: A manufacturing method for a semiconductor device embedded substrate, includes: a first step including: a step of forming a connection terminal on an electrode pad formed on a semiconductor integrated circuit, a step of forming a first insulating layer on the semiconductor integrated circuit, a step of providing a plate-like body on the first insulating layer, a step of exposing a part of the connection terminal, and a step of removing the plate-like body to manufacture a semiconductor device; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; and a fifth step of forming a first wiring pattern electrically connected to the exposed portion on a surface of each of the first insulating layer and the second insulating layer.

Abstract: A method for manufacturing a semiconductor device has preparation step of preparing a semiconductor substrate having a plurality of semiconductor chip formation regions and a scribe region arranged between the plurality of the semiconductor chip formation regions and including a substrate cutting position, a semiconductor chip formation step of forming semiconductor chips having electrode pads on the plurality of semiconductor chip formation regions, a first insulation layer formation step of forming a first insulation layer on the semiconductor chips and the scribe region of the semiconductor substrate, a second insulation layer formation step of forming a second insulation layer on the first insulation layer except for a region corresponding to the substrate cutting position, and a cutting step of cutting the semiconductor substrate at the substrate cutting position.

Abstract: In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction.

Abstract: The present invention relates to a semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, and an object of the invention is to provide the semiconductor chip and its manufacturing method in which the reduction in size may be attempted. It includes a semiconductor chip 15, an external connection terminal pad 18 electrically connected to the semiconductor chip 15, and an encapsulation resin 16 encapsulating the semiconductor chip 15, wherein a wiring pattern 12 on which the external connection terminal pad 18 is formed is provided between the semiconductor chip 15 and the external connection terminal pad 18, and the semiconductor chip 15 is flip-chip bonded to the wiring pattern 12.

Abstract: A wiring board includes an insulating layer in which a semiconductor chip is embedded, and a wiring structure connected to the semiconductor chip. A reinforcing member reinforcing the insulating layer is embedded in the insulating layer. This enables reduction in a thickness of the wiring board and a suppression of warpage of the wiring board.

Abstract: There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.

Abstract: A disclosed device includes a manufacturing method of semiconductor device including preparing a semiconductor substrate including semiconductor chip forming regions, scribing regions surrounding these regions, and cutting regions formed in the scribing regions and narrower than the scribing regions, forming check patterns and semiconductor chips, forming a resist film, forming through grooves narrower than the scribing regions and wider than the check patterns and the cutting regions, removing the check patterns with a wet blast process using the resist film and collectively forming grooves at portions of a protection film and the semiconductor substrate facing the through grooves, removing the resist film, forming internal connection terminals on the contacting faces, forming an insulating resin layer, forming a wiring forming face by removing until connecting faces are exposed, forming wiring patterns, and cutting the semiconductor substrate, the insulating resin layer, and a solder resist layer to separat

Abstract: A semiconductor device includes a reinforcement plate having an accommodating hole and a through hole extending from a first surface to a second surface, a semiconductor chip including a chip core and a pad formed on a pad surface of the chip core, the semiconductor chip disposed in the accommodating hole with the pad surface flush with the first surface, the chip core having substantially the same thickness as the reinforcement plate and including a semiconductor substrate, a through-hole electrode disposed in the through hole, resin sealing the semiconductor chip and the reinforcement plate, a interconnection pattern disposed on the first-surface side of the reinforcement plate to connect between the through-hole electrode and the pad, and a interconnection pattern disposed on the second-surface side of the reinforcement plate to be connected to the through-hole electrode, wherein the reinforcement plate is made of the same material as the semiconductor substrate.

Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.

Abstract: In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction.

Abstract: Insulating films (13, 14) are formed on the surface of a semiconductor wafer (30) on the side on which a plurality of devices are formed. Then, conductor layers (15, 16) are formed to cover opening portions from which electrode pads (12) of each device are exposed. Furthermore, a resist layer (R2) is formed to have opening portions from which terminal formation portions of the conductor layer are exposed, and metal posts (17) are formed on the terminal formation portions of the conductor layer (16) using the resist layer (R2) as a mask. Then, thinning of the semiconductor wafer (30) is performed to a predetermined thickness by grinding the back surface thereof. Thereafter, the resist layer (R2) is removed; an unnecessary portion (15) of the conductor layer is further removed; sealing with sealing resin is performed with the top portions of the metal posts (17) being exposed; metal bumps are bonded to the top portions of the metal posts (17); and the semiconductor wafer is divided into each device.

Abstract: There are provided the steps of forming a bump 104 having a protruded portion 104B on an electrode pad 103 formed on a substrate 101A, forming an insulating layer 105 on the substrate 101A and exposing a part of the protruded portion 104B to an upper surface of the insulating layer 105, forming a first conductive pattern 107 by using a depositing process in the upper surface of the insulating layer 105 and an exposed part of the protruded portion 104B, carrying out electrolytic plating by using the first conductive pattern 107 as a feeding layer, thereby forming a second conductive pattern 108, and patterning the second conductive pattern 108 to form a conductive pattern 106 connected to the bump 104.

Abstract: A method of forming an electrode on a semiconductor wafer by plating is disclosed that is able to reliably prevent leakage of a plating solution during the plating process. The plating method comprises the steps of forming a conductive layer on a semiconductor wafer; forming a negative resist layer on the conductive layer; exposing a center portion of the negative resist layer; exposing a peripheral region of the negative resist layer after the step of exposing the center portion of the negative resist layer; developing the exposed negative resist layer to form a predetermined plating pattern; and performing plating on the plating pattern.

Abstract: A semiconductor chip is characterized by a structure including a semiconductor chip on which electrode pads are formed, bumps which are formed on the respective electrode pads and which have projection sections, an insulating layer formed on the semiconductor chip, and a conductive pattern to be connected to the bumps, wherein extremities of the projection sections are inserted into the conductive pattern and the inserted extremities are flattened.

Abstract: A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole, a first protrusion protruding from the base member, which is formed on a first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, which is formed on a second end of the penetrating part. The first protrusion and second protrusion are wider than a diameter of the through-hole.

Abstract: It is configured to comprise a semiconductor chip 110, a resin member 106 for forming a cavity 109 in which this semiconductor chip 110 is installed, and wiring 105 constructed of pattern wiring 105b formed so as to be exposed to an upper surface 106b of this resin member 106 and also connected to the semiconductor chip 110 and a post part 105a in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to a lower surface 106a of the resin member 106.

Abstract: It is a semiconductor device that has a semiconductor chip on which an electrode pad is formed, an electric connection member formed on the electrode pad, an insulating layer formed on the semiconductor chip, and an electrically conductive pattern connected to the electric connection member. An opening portion corresponding to the electric connection member is formed in the conductive pattern. The conductive pattern is electrically connected to the electric connection member by an electrically conducting paste embedded in the opening portion.

Abstract: Resist films 19 for liftoff are formed on an insulating layer 12 corresponding to a wiring formation region A so as to expose the insulating layer 12 corresponding to formation positions of first seed layers 14 and thereafter, metal films 21 are formed. Then, the resist films 19 for liftoff are removed and the first and second seed layers 14, 22 are formed. Thereafter, conductive metals 15 are precipitated and grown on the first seed layers 14 by an electrolytic plating method and thereafter the second seed layers 22 are removed and thereby, wirings 13 made of the first seed layers 14 and the conductive metals 15 are formed.

Abstract: The present invention relates to a manufacturing method of a semiconductor device having a size approximately same as the size of a semiconductor chip when viewed in a plan view, in which the semiconductor chip is flip-chip bonded to a wiring pattern, and an object of the invention is to provide the manufacturing method of a semiconductor device which allows reduction in the number of process steps to realize the minimization of manufacturing cost. An insulating resin 13 is formed so as to cover a plurality of internal connection terminals 12 and a surface of a plurality of semiconductor chips 11 on which the plurality of internal connection terminals are provided, then a metal layer 33 for forming a wiring pattern is formed over the insulating resin 13, and by pressing the metal layer 33, the metal layer 33 and the plurality of internal connection terminals 12 are pressure-bonded.

Abstract: A wiring board includes: a semiconductor chip; an insulating layer in which the semiconductor chip is embedded; a wiring connected to the semiconductor chip; and reinforcing layers for reinforcing the insulating layer, the reinforcing layers respectively formed on a front face side of the insulating layer and a rear face side of the insulating layer.