Abstract: Provided is a light-emitting device including an organic light-emitting element and a control unit that controls the organic light-emitting element. The organic light-emitting element includes a first electrode, a second electrode, and an organic light-emitting layer which is disposed between the first electrode and the second electrode and in which separation of charges occurs due to incidence of excited light. The control unit changes a potential difference between the first electrode and the second electrode so that recoupling of the charges occurs, in a second period after passage of a delay period from a first period in which the excited light is incident to the organic light-emitting layer.

Abstract: A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.

Abstract: A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.

Abstract: A joined body is formed by joining end surfaces of two joining members to each other by a friction welding. The joined body includes a hollow portion formed on at least one of the two joining members, the hollow portion being configured to have an opening at the joining face between the two joining members. The joined body also includes an annular groove portion formed on an inner circumferential surface of the hollow portion at a position separated from a joining face in an axial direction.

Abstract: A joined body formed by joining end surfaces of two joining members to each other by a friction welding, the joined body includes a hollow portion formed on at least one of the two joining members, the hollow portion being configured to have an opening at the joining face between the two joining members; and an annular groove portion formed on an inner circumferential surface of the hollow portion at a position separated from a joining face in an axial direction.

Abstract: A hydraulic cylinder includes a piston unit inside a cylinder to be free to slide within the cylinder; and a piston rod having the piston unit fixed to one end thereof and another end thereof projecting from the cylinder. The piston unit is inserted into a small diameter portion of the piston rod with an end surface thereof fixedly contacting a shoulder end surface of the piston rod. A round portion is formed as an annular concave in a base end portion outer periphery of the small diameter portion of the piston rod. A tapered portion is formed on an inner periphery of the piston unit from the end surface in alignment with a portion formed by concaving the small diameter portion. A length of the tapered portion in a piston unit axial direction is equal or greater than a length of the concave portion in a piston rod axial direction.

Abstract: A bracket (20) that is fixed to a band (10) mounted on an outer peripheral surface (2a) of a cylinder tube (2) supports a pipe (4). The band (10) includes a first tab (11a) projecting outward in a radial direction and a second tab (11b) projecting outward in the radial direction. The bracket (20) supporting the pipe (4) is formed with an inverted U-shaped cross-section constituted by a pair of leg plate portions (20a) and a top plate portion (20b) formed integrally with the leg plate portions (20a) to join the leg plate portions (20a). The pair of leg plate portions (20a) are fixed to the first tab (11a) and the second tab (11b) by a bolt, and a small and lightweight pipe fixing structure is thus realized.

Abstract: A bracket (20) that is fixed to a band (10) mounted on an outer peripheral surface (2a) of a cylinder tube (2) supports a pipe (4). The band (10) includes a first tab (11a) projecting outward in a radial direction and a second tab (11b) projecting outward in the radial direction. The bracket (20) supporting the pipe (4) is formed with an inverted U-shaped cross-section constituted by a pair of leg plate portions (20a) and a top plate portion (20b) formed integrally with the leg plate portions (20a) to join the leg plate portions (20a). The pair of leg plate portions (20a) are fixed to the first tab (11a) and the second tab (11b) by a bolt, and a small and lightweight pipe fixing structure is thus realized.

Abstract: A hydraulic cylinder includes a piston unit inside a cylinder to be free to slide within the cylinder; and a piston rod having the piston unit fixed to one end thereof and another end thereof projecting from the cylinder. The piston unit is inserted into a small diameter portion of the piston rod with an end surface thereof fixedly contacting a shoulder end surface of the piston rod. A round portion is formed as an annular concave in a base end portion outer periphery of the small diameter portion of the piston rod. A tapered portion is formed on an inner periphery of the piston unit from the end surface in alignment with a portion formed by concaving the small diameter portion. A length of the tapered portion in a piston unit axial direction is equal or greater than a length of the concave portion in a piston rod axial direction.

Abstract: Disclosed is an antibody which can recognize BRAK (CXCL14). Also disclosed is use of the antibody. The antibody can recognize a polypeptide comprising an amino acid sequence depicted in SEQ ID NO:1 or 2, a derivative thereof, or a partial peptide of the polypeptide or the derivative.

Abstract: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.

Abstract: A semiconductor device includes a plurality of semiconductor chips and a memory device. The semiconductor chips are provided in a package. Each of the semiconductor chips includes a memory cell array having memory cells which stores data, an output buffer which outputs data read from the memory cell array to an exterior of the semiconductor chip and a control circuit which controls driving power of the output buffer. The memory device stores the number of semiconductor chips provided in the package. The control circuit controls the driving power according to the number of semiconductor chips stored in the memory device.

Abstract: A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip.

Abstract: A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter.

Abstract: A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor, a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate, a dummy gate driving circuit controlling a potential of the control gate of the dummy gate, and a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing t

Abstract: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.