Patents by Inventor Takahiko Hara
Takahiko Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7560766Abstract: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.Type: GrantFiled: January 31, 2008Date of Patent: July 14, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Minori Kajimoto, Mitsuhiro Noguchi, Hiroshi Maejima, Takahiko Hara
-
Publication number: 20090131634Abstract: Mouse PCLP1 was identified by expression cloning with the use of a monoclonal antibody against a surface antigen of a cell line derived from mouse AGM. By fractionating PCLP1-positive/CD45-negative cells and culturing them in vitro, it was clarified that these cells differentiate into endothelial-like cells, angioblast-like cells, and hematopoietic cells. By transferring the PCLP1-positive/CD45-negative cells into a mouse defective in the hematopoietic function, the hematopoietic system was reconstructed over a long period of time. These facts indicate that the PCLP1-positive/CD45-negative cells contain mammalian hemangioblasts capable of expressing the activity as long-term repopulating hematopoietic stem cells (LTR-HSC). The present invention provides a method for preparing a cell fraction containing hemangioblasts, the cell fraction prepared by the method, and use of this cell fraction.Type: ApplicationFiled: October 17, 2008Publication date: May 21, 2009Inventors: Atsushi MIYAJIMA, Takahiko HARA
-
Patent number: 7532520Abstract: A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter.Type: GrantFiled: July 16, 2007Date of Patent: May 12, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Kosuke Yanagidaira, Koichi Fukuda, Takahiko Hara
-
Publication number: 20090008680Abstract: A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip.Type: ApplicationFiled: July 11, 2008Publication date: January 8, 2009Inventor: Takahiko HARA
-
Patent number: 7455962Abstract: Mouse PCLP1 was identified by expression cloning with the use of a monoclonal antibody against a surface antigen of a cell line derived from mouse AGM. By fractionating PCLP1-positive/CD45-negative cells and culturing them in vitro, it was clarified that these cells differentiate into endothelial-like cells, angioblast-like cells, and hematopoietic cells. By transferring the PCLP1-positive/CD45-negative cells into a mouse defective in the hematopoietic function, the hematopoietic system was reconstructed over a long period of time. These facts indicate that the PCLP1-positive/CD45-negative cells contain mammalian hemangioblasts capable of expressing the activity as long-term repopulating hematopoietic stem cells (LTR-HSC). The present invention provides a method for preparing a cell fraction containing hemangioblasts, the cell fraction prepared by the method, and use of this cell fraction.Type: GrantFiled: November 7, 2000Date of Patent: November 25, 2008Assignee: Toudai TLO. Ltd.Inventors: Atsushi Miyajima, Takahiko Hara
-
Publication number: 20080205137Abstract: A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter.Type: ApplicationFiled: July 16, 2007Publication date: August 28, 2008Inventors: Kosuke Yanagidaira, Koicho Fukuda, Takahiko Hara
-
Patent number: 7408262Abstract: A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip.Type: GrantFiled: January 29, 2007Date of Patent: August 5, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Takahiko Hara
-
Publication number: 20080149993Abstract: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.Type: ApplicationFiled: January 31, 2008Publication date: June 26, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Minori Kajimoto, Mitsuhiro Noguchi, Hiroshi Maejima, Takahiko Hara
-
Patent number: 7339227Abstract: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.Type: GrantFiled: July 18, 2006Date of Patent: March 4, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Minori Kajimoto, Mitsuhiro Noguchi, Hiroshi Maejima, Takahiko Hara
-
Publication number: 20080019182Abstract: A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter.Type: ApplicationFiled: July 16, 2007Publication date: January 24, 2008Inventors: Kosuke Yanagidaira, Koichi Fukuda, Takahiko Hara
-
Publication number: 20080008004Abstract: A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip.Type: ApplicationFiled: January 29, 2007Publication date: January 10, 2008Inventor: Takahiko Hara
-
Publication number: 20070279981Abstract: A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor, a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate, a dummy gate driving circuit controlling a potential of the control gate of the dummy gate, and a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing tType: ApplicationFiled: June 28, 2007Publication date: December 6, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Takumi ABE, Hiroshi Maejima, Koichi Fukuda, Takahiko Hara
-
Publication number: 20070246807Abstract: A semiconductor device includes a plurality of semiconductor chips and a memory device. The semiconductor chips are provided in a package. Each of the semiconductor chips includes a memory cell array having memory cells which stores data, an output buffer which outputs data read from the memory cell array to an exterior of the semiconductor chip and a control circuit which controls driving power of the output buffer. The memory device stores the number of semiconductor chips provided in the package. The control circuit controls the driving power according to the number of semiconductor chips stored in the memory device.Type: ApplicationFiled: April 23, 2007Publication date: October 25, 2007Inventors: Takahiko Hara, Midori Morooka
-
Patent number: 7239556Abstract: A NAND-structured flash memory comprises a memory cell array wherein plural memory strings are arranged in matrix form, each of the memory cell strings including plural nonvolatile memory cells, the first conducting paths of the memory cells being connected in series, at least one of the memory cells having a function other than an external data storing function, plural first selection transistors having second conducting paths, and one end of the second conducting paths being connected to one end of the series of the first conducting paths, respectively, plural bit lines connected to the other end of the second conducting paths, plural second selection transistors having third conducting paths, and one end of the third conducting paths being connected to one end of the series of the first conducting paths, respectively, and a source line connected to the other end of the third conducting paths.Type: GrantFiled: February 15, 2005Date of Patent: July 3, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takumi Abe, Hiroshi Maejima, Koichi Fukuda, Takahiko Hara
-
Patent number: 7145199Abstract: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.Type: GrantFiled: November 9, 2004Date of Patent: December 5, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Minori Kajimoto, Mitsuhiro Noguchi, Hiroshi Maejima, Takahiko Hara
-
Publication number: 20060267069Abstract: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.Type: ApplicationFiled: July 18, 2006Publication date: November 30, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Minori Kajimoto, Mitsuhiro Noguchi, Hiroshi Maejima, Takahiko Hara
-
Patent number: 7132508Abstract: A novel CC chemokine which is from a mammal, reagents related thereto including purified proteins, specific antibodies, and nucleic acids encoding said chemokine. A chemokine receptor is also provided. Methods of using said reagents and diagnostic kits are also provided.Type: GrantFiled: November 13, 2002Date of Patent: November 7, 2006Assignee: Schering CorporationInventors: Daniel J. Dairaghi, Takahiko Hara, Atsushi Miyajima, Thomas J. Schall, Wei Wang, Akihiko Yoshimura
-
Publication number: 20060153802Abstract: A novel CC chemokine which is from a mammal, reagents related thereto including purified proteins, specific antibodies, and nucleic acids encoding said chemokine. A chemokine receptor is also provided. Methods of using said reagents and diagnostic kits are also provided.Type: ApplicationFiled: March 20, 2006Publication date: July 13, 2006Inventors: Daniel Dairaghi, Takahiko Hara, Atsushi Miyajima, Thomas Schall, Wei Wang, Akihiko Yoshimura
-
Patent number: 7050346Abstract: A non-volatile semiconductor memory device includes a cell array in which electrically rewritable and non-volatile memory cells are arranged, and a sense amplifier circuit configured to read and write data in association with the cell array, wherein the sense amplifier circuit includes: differential amplifier having first and second input nodes and configured to amplify a difference voltage between the first and second input nodes; a data transfer circuit configured to selectively connect the first input node to a bit line in the cell array; a reference voltage setting circuit configured to apply a reference voltage to the second input node of the differential amplifier; and a data storing circuit configured to temporarily hold a loaded write data at the first input node of the differential amplifier, and control the reference voltage at the second input node of the differential amplifier in correspondence with the write data held therein.Type: GrantFiled: July 16, 2004Date of Patent: May 23, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Maejima, Takahiko Hara
-
Patent number: 6973002Abstract: A semiconductor integrated circuit is composed of a memory array, sense amplifiers, a first and second drive circuits, and a sense amplifier control circuit. The memory cell array has memory cells arranged in matrix form. The sense amplifiers amplify a signal read from the memory cells. The sense amplifiers include N channel sense amplifiers each composed of an N channel MOS transistor and P channel sense amplifiers each composed of a P channel MOS transistor. The first and second drive circuits each include an N channel MOS transistor that drives the N channel sense amplifiers or the P channel sense amplifiers, respectively. The first and second drive circuits are arranged adjacent to the sense amplifiers. The sense amplifier control circuit supplies a common control signal to both gate electrodes of the N channel MOS transistors included in the first and second drive circuits.Type: GrantFiled: September 22, 2003Date of Patent: December 6, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Takahiko Hara, Masahiro Yoshihara