Abstract: A voltage generation circuit and a semiconductor memory device capable of decreasing the layout size and the consumed current are provided. A voltage generation circuit includes a plurality of voltage generation units which generate different output voltages based on an external power supply voltage. Each of the plurality of voltage generation unit comprises a plurality of resistors that are connected in series to detect the output voltages. At least one of these resistors is coupled to and shared by the plurality of voltage generation units.

Abstract: The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.

Abstract: An optical waveguide is an optical waveguide including a semiconductor quantum well structure, the optical waveguide including a first region in which the semiconductor quantum well structure is not disordered and a second region in which the semiconductor quantum well structure is disordered. The first region has a first bandgap wavelength, the second region has a second bandgap wavelength, and a region in which the semiconductor quantum well structure is disordered in such a manner that a bandgap wavelength continuously decreases from the first bandgap wavelength to the second bandgap wavelength is provided between the first region and the second region.

Abstract: An electrostatic chuck for supporting a substrate includes a dielectric member having a substrate support surface, a groove formed on an upper surface of the dielectric member, and a plurality of electrode layer segments to which a high voltage is applied. The plurality of electrode layer segments are located in the dielectric member. At least one electrode layer segment of the plurality of electrode layer segments is located under a portion of the upper surface of the dielectric member where the groove is not formed. None of the plurality of electrode layer segments is located at a position under the groove and higher than the at least one electrode layer segment.

Abstract: The present invention provides an initial setting device of semiconductor memory, which includes a voltage detection part, a first non-volatile memory device, a control unit, and a determination unit. The voltage detection part detects the voltage of the power supply. The first non-volatile memory device stores the first setting information, which is used for setting the operation condition of the semiconductor memory. The control unit reads the first setting information from the first non-volatile memory device according to the voltage level of the detected power supply. The determination unit determines whether first setting information that was read is valid. The reading condition of the first setting information is changed and the first setting information is read simultaneously every time the first setting information is determined as invalid until the first setting information is determined as valid.

Abstract: A semiconductor memory device includes a plurality of word lines, a bit line, a memory cell array, a sense amplifier, and an adjustment unit. The memory cell array includes a plurality of memory cells, wherein each of the plurality of memory cells is connected to one of the plurality of word lines and the bit line. The sense amplifier is connected to the bit line. The adjustment unit counts the number of erroneously-read memory cells whose read values are different from an expected value during a data reading operation of the memory cell while changes a parameter related to a condition of a sensing operation of the sense amplifier. The adjustment unit adjusts a value of the parameter so that the number of erroneously-read memory cells is the minimum.

Abstract: A voltage generation circuit and a semiconductor memory device capable of decreasing the layout size and the consumed current are provided. A voltage generation circuit includes a plurality of voltage generation units which generate different output voltages based on an external power supply voltage. Each of the plurality of voltage generation unit comprises a plurality of resistors that are connected in series to detect the output voltages. At least one of these resistors is coupled to and shared by the plurality of voltage generation units.

Abstract: There is a plasma processing apparatus comprising: a plasma processing chamber; an electrostatic chuck disposed on a base, and comprising a substrate mounting portion and an edge ring mounting portion; and at least one of a first power supply part that supplies power to the substrate mounting portion and a second power supply part that supplies power to the edge ring mounting portion, wherein the first power supply part comprises: a first electrode layer formed on the substrate mounting portion; a first adsorption electrode layer disposed under the first electrode layer; and a first bias power source connected to the first electrode layer, and wherein the second power supply part comprises: a second electrode layer formed on the edge ring mounting portion; a second adsorption electrode layer disposed under the second electrode layer; and a second bias power source connected to the second electrode layer.

Abstract: A plasma processing apparatus includes a plasma processing chamber, a base in the plasma processing chamber, and an electrostatic chuck on the base. The electrostatic chuck includes a dielectric structure having a substrate support surface and a ring support surface, an electrostatic clamp electrode inside the dielectric structure, a bias electrode inside the dielectric structure and below the electrostatic clamp electrode, and at least one conductive structure at least partially located inside the dielectric structure. The dielectric structure has a through-hole extending through the dielectric structure from the substrate support surface or the ring support surface to a lower surface of the dielectric structure. The at least one conductive structure surrounds the through-hole and extends upward from a same level as the bias electrode in a height direction or from a higher level than the bias electrode.

Abstract: A substrate support is arranged in a processing container. The substrate support includes an electrostatic chuck provided with a first support surface for supporting a substrate, provided with a first electrode and a second electrode which are arranged in the electrostatic chuck sequentially from the first support surface, and made of a dielectric material, and a base configured to support the electrostatic chuck. The second electrode is arranged at a position having a distance to the first support surface that is equal to or less than a distance to the base. A voltage for attracting the substrate is applied to the first electrode and bias power is supplied to the second electrode.

Abstract: A semiconductor memory device is provided to suppress occurrence of disturbance regardless of the position of the activated word line. The semiconductor memory device includes a plurality of word lines, a bit line, a plurality of memory cells connected to the bit line and one of the plurality of word lines, a sense amplifier connected to the bit line, and a control portion. The control portion is configured to control timing of activating the sense amplifier. When a position of an activated word line among the plurality of word lines is closer to the sense amplifier, the control portion controls the timing of activating the sense amplifier to be delayed more.

Abstract: The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.

Abstract: A pseudo-static random access memory is provided herein, which may improve the speed of data transmission. After a first delay from a command and a row address being input in a first operation, the pseudo-static random access memory inputs or outputs the data in the memory cells corresponding to the input row address and the input column address, which includes a control unit controlling a delay in the second operation less than the initial delay when a specific condition is satisfied. The second operation is executed after the first operation.

Abstract: A semiconductor memory device is provided. The semiconductor memory device can suppress increases in power consumption. As a result, damage to the data normally caused by row hammer problem can be prevented. The semiconductor memory device includes a control unit. The control unit controls a refresh operation for a memory to be performed at any interval, wherein there are a plurality of possible intervals. When read/write access to the memory is required, the control unit controls the refresh operation for the memory to be performed with a shortest interval among the intervals, until a predetermined condition is met.

Abstract: Between a housing and a position ensuring member, provided are: a first locking mechanism that locks move of the position ensuring member at a standby position in an ensuring-operation direction toward a fitting assured position when a lever member is not at a completely fitted position; and a second locking mechanism that locks move of the position ensuring member at the fitting ensured position in an ensuring-release direction that is a reverse direction of the ensuring-operation direction when the lever member is at the completely fitted position. Between the lever member and the position ensuring member, provided is a locking release mechanism that releases a locked state of the position ensuring member with the first locking mechanism when the lever member comes at the completely fitted position.

Abstract: A temperature sensing circuit adapted for a memory device and including an oscillator, a count circuit, a control circuit, a sense circuit and a select circuit is provided. The oscillator provides an oscillation signal. The count circuit counts the oscillation signal to generate a first count signal, and generates a second count signal. The count circuit performs a logic operation on the second count signal to generate an enable signal and a sensing adjustment signal. The sense circuit generates a reference temperature voltage by dividing a reference voltage according to the sensing adjustment signal, and compares the reference temperature voltage and a monitor voltage according to the enable signal to generate a determination signal.

Abstract: A power supply control circuit that is able to reliably discharge to the internal power supply, even when the external power supply is cut off instantaneously. The power supply control circuit includes a voltage detection unit, an internal power supply generation unit, and a control unit. The voltage detection unit detects the voltage of the external power supply. The internal power supply generation unit generates the internal power supply, according to the external power supply. The control unit controls the discharging to the internal power supply according to at least the second control signal among the first control signal and the second control signal, when the detected voltage of the external power supply drops below the predetermined value.

Abstract: A semiconductor memory device is provided to suppress occurrence of disturbance regardless of the position of the activated word line. The semiconductor memory device includes a plurality of word lines, a bit line, a plurality of memory cells connected to the bit line and one of the plurality of word lines, a sense amplifier connected to the bit line, and a control portion. The control portion is configured to control timing of activating the sense amplifier. When a position of an activated word line among the plurality of word lines is closer to the sense amplifier, the control portion controls the timing of activating the sense amplifier to be delayed more.

Abstract: A service plug includes first and second main terminals, first and second signal terminals, a lock part that locks a lever to a second connector housing to regulate rotation of the lever in a state in which the lever is positioned at a half-engaged position between a completely engaged position and a non-engaged position, and a lock releasing part that releases a lock state. A configuration is made such that, as the lever is rotated from the completely engaged position to the half-engaged position, part of a plurality of contact pieces of the second main terminal that is brought into elastic contact with the first main terminal at a position displaced in an approaching direction, and the other part of the contact pieces maintains elastic contact at a position that is not displaced in the approaching direction and a separating direction.

Abstract: A connector housing includes a housing main body, a seal element configured to tightly seal a gap between an outer circumferential surface of an electric wire section of a terminal-equipped electric wire and an inner circumferential surface of the housing main body, and a rear holder which is a lid element configured to be attached to the housing main body so as to close the rear side opening and has a passage hole and a protrusion, the passage hole allowing the electric wire section to pass therethrough and having a larger opening area than a radial cross section area of the electric wire section, wherein the protrusion protrudes from a portion of an inner circumferential surface of the passage hole in a circumferential direction with a protrusion length, the protrusion length being adapted to an inner circumference position of a sealing through hole.