Abstract: A semiconductor memory that assigns M data groups, each data group including N data, to a first address, where M and N are integers equal to or larger than 2; and wherein L data among N data is designated by a second address indicating a position of the data groups and the L data is read from the designated position, where L is an integer and L<N.

Abstract: A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes the internal address and selects a memory unit region. The plurality of memory unit regions store data arranged in a first direction from among two-dimensionally arranged data according to a least-significant bit group of the internal address and store data arranged in a second direction from among the two-dimensionally arranged data according to a most-significant bit group of the address. The internal address control unit successively generates an internal address corresponding to the scan direction according to a scan direction control signal which controls a plurality of scan directions including at least an oblique direction of the two-dimensionally arranged data.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: A semiconductor integrated circuit includes a plurality of terminals, a first latch configured to, upon being uniquely specified by a first predetermined number of bits that are part of a plurality of bits entered through the terminals, store a second predetermined number of bits that are at least part of remaining bits left after excluding the first predetermined number of bits from the plurality of bits, and a second latch configured to, upon being uniquely specified by a third predetermined number of bits that are part of the plurality of bits entered through the terminals, store a fourth predetermined number of bits that are at least part of remaining bits left after excluding the third predetermined number of bits from the plurality of bits, wherein the first predetermined number is different from the third predetermined number, and the second predetermined number is different from the fourth predetermined number.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: A semiconductor device includes a first input circuit to which a first supply voltage is supplied, a second input circuit to which a second supply voltage that is lower than the first supply voltage is supplied, and a control circuit which activates the first input circuit in a first mode and activates the second input circuit in a second mode. The control circuit controls the first input circuit and the second input circuit such that the first input circuit and the second input circuit are activated during a certain time period when switching between the first mode and the second mode.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: A center cluster panel 2 is formed with a projected portion 20 including an upper panel 21 extended to a vehicle rear side and disposed at an uppermost portion thereof, a curved face panel 22 connected to a rear portion of the upper panel 21 and directed to a vehicle front side by being bent from the connected portion 24, and a lower panel 23 connected to the curved face panel 22, extended to a front side and disposed on a vehicle lower side of the upper panel 21. The upper panel 21 and the lower panel 23 are formed such that respective wall thicknesses t1 and t2 are uniform. The wall thickness t1 of the upper panel 21 is made to be thicker than the wall thickness t2 of the lower panel 23. The curved face panel 22 is formed such that a wall thickness t3 thereof is equal to the wall thickness t1 of the upper panel 21 at the portion 24 connected with the upper panel 21 and formed such that the more proximate to the lower panel 23 from the connected portion 24, the more thinned the wall thickness t3 gradually.

Abstract: A resin made air bag door includes a main portion having a welding face to be attached to an inner surface of a dashboard having a thickness of 2.0 mm or less at a welding area, by vibration welding, a plurality of welding ribs formed on the welding face in a vibrating direction of the vibration welding, and at least one bridging rib formed on the welding face of the main portion and extending in a direction crossing across the welding ribs. The plurality of welding ribs includes a welding portion to be melted at the time of vibration welding and a bonding portion to be bonded to the inner surface of the dashboard, remaining at the time of vibration welding. A width of a tip end of the bonding portion is equal to or less than 3 mm.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: A semiconductor memory that assigns M data groups, each data group including N data, to a first address, where M and N are integers equal to or larger than 2; and wherein L data among N data is designated by a second address indicating a position of the data groups and the L data is read from the designated position, where L is an integer and L<N.

Abstract: A semiconductor memory device comprises: a memory cell group, the memory cell including a number of which is 2n, the n being a positive integer; and a first decoder provided with respect to each of the memory cell groups and a second decoder. The first decoder activates a word line by the memory cell group based upon a first address and an n bit in a second address and the second decoder activates a bit line based upon the second address.

Abstract: An outer tube part 8 and an inner tube part 6 which is disposed in an interior of the outer tube part 8 are provided in an air-conditioning duct system which is connected to an air flow path downstream side of a vehicle air-conditioning system, and a side branch type silencer chamber 9 is defined by an inner circumferential surface of the outer tube part 8 and an outer circumferential surface of the inner tube part 6. In addition, an axis of at least a portion of the outer tube part 8 which confronts the inner tube part 6 and an axis of the inner tube part 6 are both made to be a straight line, and a register functioning part is provided in an interior of a portion of the outer tube part 8 which lies further downstream in an air flow path than the inner tube part 6.

Abstract: Operation control circuits start a first operation of any of memory cores in response to a first operation command, start a second operation of any of the memory cores in response to a second operation command, and terminate the first operation and continue the second operation in response to a termination command to terminate operations of the plurality of memory cores. For example, the semiconductor memory is mounted on a system together with a controller accessing the semiconductor memory. The termination of the operation in response to the termination command is judged in accordance with an operation state of the memory core. Accordingly, it is possible to terminate the operation of the memory core requiring the termination of operation without specifying the memory core from outside.

Abstract: An airbag apparatus for protecting knees is provided. A breakable portion is provided in a wall of a glove compartment door for opening and closing an opening of a glove compartment. The wall faces a vehicle passenger compartment. An airbag case for housing an airbag, which is inflated by inflation fluid, is installed inside the wall. A front part of the airbag case is caused to function as a pressure receiving portion for receiving a pressure of the inflation fluid through the inflating airbag, thereby generating a reaction force advancing toward the rear side of the vehicle, so that the breakable portion is broken by the airbag inflating toward the rear side of the vehicle. The airbag is caused to protrude from the glove compartment door to the rear side of the vehicle through the breakable portion.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: In a clip attaching seat 1 integrally provided to a vehicular interior molded product and attached with a clip having a locking head portion of a bulged shape above a neck portion, on a face of a seating portion 11 in a plate-like shape formed with a clip locking hole 12, ribs (14 through 16) having widths the same as a plate thickness thereof are formed. Thereby, a rigidity of the thin-walled seating portion 11 is ensured while making a wall thickness of a total of the clip attaching seat 1 constant.

Abstract: A center cluster panel 2 is formed with a projected portion 20 including an upper panel 21 extended to a vehicle rear side and disposed at an uppermost portion thereof, a curved face panel 22 connected to a rear portion of the upper panel 21 and directed to a vehicle front side by being bent from the connected portion 24, and a lower panel 23 connected to the curved face panel 22, extended to a front side and disposed on a vehicle lower side of the upper panel 21. The upper panel 21 and the lower panel 23 are formed such that respective wall thicknesses t1 and t2 are uniform. The wall thickness t1 of the upper panel 21 is made to be thicker than the wall thickness t2 of the lower panel 23. The curved face panel 22 is formed such that a wall thickness t3 thereof is equal to the wall thickness t1 of the upper panel 21 at the portion 24 connected with the upper panel 21 and formed such that the more proximate to the lower panel 23 from the connected portion 24, the more thinned the wall thickness t3 gradually.

Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

Abstract: A semiconductor integrated circuit includes a plurality of terminals, a first latch configured to, upon being uniquely specified by a first predetermined number of bits that are part of a plurality of bits entered through the terminals, store a second predetermined number of bits that are at least part of remaining bits left after excluding the first predetermined number of bits from the plurality of bits, and a second latch configured to, upon being uniquely specified by a third predetermined number of bits that are part of the plurality of bits entered through the terminals, store a fourth predetermined number of bits that are at least part of remaining bits left after excluding the third predetermined number of bits from the plurality of bits, wherein the first predetermined number is different from the third predetermined number, and the second predetermined number is different from the fourth predetermined number.