Patents by Inventor Takahiro Hayashi

Takahiro Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170030785
    Abstract: The present invention provides a stress measuring method including: irradiating a photoelastic product including a measurement subject with light penetrating a linear polarizing film and a phase difference film in this order, and detecting reflected light from the product which is derived from the light via the phase difference film and the linear polarizing film in this order, in which in-plane retardation Re (550) of the phase difference film with light having a wavelength of 550 nm satisfies 100 nm?Re (550 nm)?700 nm, and in-plane retardation Re (450) of the phase difference film with light having a wavelength of 450 nm satisfies Re (450)/Re (550)?0.9, a stress measuring member including the linear polarizing film and the phase difference film, and a stress measuring set including the stress measuring member and a stress displaying member including a photoelastic layer.
    Type: Application
    Filed: October 13, 2016
    Publication date: February 2, 2017
    Applicant: FUJIFILM Corporation
    Inventor: Takahiro HAYASHI
  • Patent number: 9516751
    Abstract: To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10. The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25. Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: December 6, 2016
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Takahiro Hayashi, Makoto Nagai, Seiji Mori, Tomohiro Nishida, Makoto Wakazono, Tatsuya Ito
  • Patent number: 9515019
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: December 6, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20160330800
    Abstract: In a microwave heating device of the present disclosure, inverter unit drives first and second microwave generators. Cooling unit cools first and second microwave generators and inverter unit. First and second waveguides supplies, to cavity, microwaves generated by first and second microwave generators. First and second microwave generators are disposed side by side in a right-left direction below a bottom surface of cavity. Inverter unit and cooling fan are disposed from the first and second microwave generators toward a front side in order, and first and second waveguides are provided so as to extend in a front-back direction from first and second microwave generators, respectively. According to the present disclosure, the microwave heating device can be further downsized in a right-left direction.
    Type: Application
    Filed: February 5, 2015
    Publication date: November 10, 2016
    Inventors: Takahiro Hayashi, Yuichi Otsuki, Seiichi Yamashita, Mikio Fukui, Toshifumi Kamiya
  • Publication number: 20160330801
    Abstract: Heating cooker (30) of the present disclosure includes convection device (35) that includes fan (14), heater (13), a first air guide, and second air guide, is communicated with heating chamber (2) through a suction port and a discharge port provided in back wall (2d) of heating chamber (2), and supplies hot air to the heating chamber (2). Fan (14) sucks air inside heating chamber (2) from the suction port into convection device (35), and sends out the air from the discharge port into heating chamber (2). Heater (13) is provided in front of fan (14), and heats the sucked air. The first air guide is provided so as to surround heater (13), and guides the heated air to the discharge port. The second air guide is provided so as to surround fan (14) and the first air guide, and guides the heated air to the discharge port. A part of the second air guide is in contact with the first air guide, and another part of the second air guide is isolated from the first air guide.
    Type: Application
    Filed: February 5, 2015
    Publication date: November 10, 2016
    Inventors: TAKAHIRO HAYASHI, YUICHI OTSUKI, SEIICHI YAMASHITA, MIKIO FUKUI, TOSHIFUMI KAMIYA
  • Publication number: 20160321850
    Abstract: A coin delivering device includes plural coin tubes, a coin base, a payout slide, a payout link, and a change slide. At least one of the coin tubes is a multiple-coin delivering coin tube from which plural coins are pulled out in one time of pulling out the payout slide. A recess portion sized for housing a coin is provided at a position corresponding to the multiple-coin delivering coin tube, on the coin base. A vertical wall portion is provided around a coin housing hole corresponding to the multiple-coin delivering coin tube, on the payout slide, protrudes to the side of the coin base, and, in a standby mode, is positioned in the recess portion of the coin base. An upper surface of the change slide corresponding to the multiple-coin delivering coin tube is positioned similar to a bottom surface of the recess portion of the coin base in height.
    Type: Application
    Filed: September 30, 2014
    Publication date: November 3, 2016
    Applicant: NIPPON CONLUX CO., LTD.
    Inventors: Yasuyuki Kodama, Takahiro Hayashi, Masashi Kondo
  • Patent number: 9485853
    Abstract: A wiring substrate according to the present invention includes a laminate of one or more insulation layers and one or more conductive layers and further includes a plurality of connection terminals formed on the laminate and spaced apart from one another, each having a step formed at the outer periphery of a first main surface opposite a contact surface in contact with the laminate, and a filling member provided in a filling manner between the connection terminals.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: November 1, 2016
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Tatsuya Ito, Seiji Mori, Takahiro Hayashi, Makoto Wakazono, Tomohiro Nishida
  • Publication number: 20160275742
    Abstract: To provide a coin dispensing device which suppresses the maximum consumption current when coins are dispensed from a plurality of coin tubes in one dispensing operation. A coin dispensing device includes a plurality of coin tubes 6 storing coins, a coin withdrawing and discharging part 8, a change part which locates a change lever 12 at a dispensing preventing position, in which the coin withdrawing and discharging part 8 is prevented from discharging the coins, by energizing a change lever solenoid 13 and locates the change lever 12 at a dispensing allowing position, in which the coin withdrawing and discharging part 8 is allowed to discharge the coins, by a biasing force of a return spring when the energizing of the change lever solenoid 13 is stopped, and a keeping means 15 which keeps a state of the change lever 12.
    Type: Application
    Filed: December 12, 2013
    Publication date: September 22, 2016
    Applicant: NIPPON CONLUX CO., LTD.
    Inventors: Takahiro HAYASHI, Masashi KONDO
  • Patent number: 9445310
    Abstract: During a transition procedure from a first communication system to a second communication system, when the priority of a second communication call, whose setup is requested, is the first priority, the second communication system does not set up the bearer of a first communication call between the second communication system and the mobile communication terminal, and notifies the first communication system that the setup of the first communication is not possible, but the setup of the second communication call is possible. When notified that the setup of the first communication is not possible, but the setup of the second communication call is possible, the first communication system aborts the handover procedure, and instructs the mobile communication terminal to switch to the second communication system by another procedure.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: September 13, 2016
    Assignee: NTT DOCOMO, INC.
    Inventors: Kenichiro Aoyagi, Yuichiro Nakamura, Hideyuki Matsutani, Mikio Iwamura, Takahiro Hayashi, Kazunori Obata
  • Patent number: 9420703
    Abstract: To provide a wiring board in which wiring conductors are securely protected by a precise and rigid dam portion formed on an outermost layer of a laminate and that is excellent in connection reliability with a semiconductor chip. A laminate that configures this wiring board includes multiple connection terminal portions and wiring conductors as a conductor layer of the outermost layer. The wiring conductors are arranged at predetermined positions, passing through between multiple connection terminal portions for flip-chip mounting a semiconductor chip. A resin insulating layer of the outermost layer of the laminate has a dam portion and a reinforcement portion. The dam portion covers the wiring conductors. The reinforcement portion is formed, between the wiring conductor and the connection terminal portion that is adjacent to the wiring conductor, lower than a height of the dam portion. The reinforcement portion is concatenated with a side surface of the dam portion.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: August 16, 2016
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Takahiro Hayashi, Makoto Nagai, Tatsuya Ito, Seiji Mori, Makoto Wakazono, Tomohiro Nishida
  • Publication number: 20160233154
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Application
    Filed: April 14, 2016
    Publication date: August 11, 2016
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Patent number: 9409152
    Abstract: A catalyst support for purification of exhaust gas includes a porous composite metal oxide, the porous composite metal oxide containing alumina, ceria, and zirconia and having an alumina content ratio of from 5 to 80% by mass, wherein after calcination in the air at 1100° C. for 5 hours, the porous composite metal oxide satisfies a condition such that standard deviations of content ratios (as at % unit) of aluminum, cerium and zirconium elements are each 19 or less with respect to 100 minute areas (with one minute area being 300 nm in length×330 nm in width) of the porous composite metal oxide, the standard deviation being determined by energy dispersive X-ray spectroscopy using a scanning transmission electron microscope equipped with a spherical aberration corrector.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: August 9, 2016
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki Kumatani, Akira Morikawa, Kae Konishi, Kimitoshi Sato, Toshitaka Tanabe, Akihiko Suda, Masahide Miura, Isao Chinzei, Hiromasa Suzuki, Takeshi Nobukawa, Takahiro Hayashi
  • Publication number: 20160169664
    Abstract: The invention provides a stress display member including: a selective reflection layer, in which the selective reflection layer includes cholesteric liquid crystal layers that are obtained by curing a liquid crystal composition including a polymerizable liquid crystal compound, and the selective reflection layer is a layer that selectively reflects circularly polarized light having any one sense of right-handed circularly polarized light and left-handed circularly polarized light in a specific wavelength, a stress display member further including a birefringence layer and optionally including a circularly polarized light separating layer, and a strain measurement method that is performed by using any one of the stress display member. According to the stress display member of the invention, it is possible to measure and visually observe a strain that occurs in a target having a large surface area at a low cost and measure a strain with high measuring accuracy.
    Type: Application
    Filed: February 19, 2016
    Publication date: June 16, 2016
    Applicant: FUJIFILM Corporation
    Inventors: Takahiro HAYASHI, Yoshihito HODOSAWA
  • Patent number: 9343460
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 17, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Patent number: 9334962
    Abstract: A waterproof gasket for a small size electronic appliance of the invention has straight portions (1A) and corner portions (1B) alternately in a peripheral direction, a main seal portion (11) and a seat seal portion (12) brought into close contact with a bottom surface of a gasket retention groove are formed, a shoulder portion (13) protruding in a width direction between said main seal portion (11) and the seat seal portion (12) so as to be brought into close contact with an inner side surface of a groove shoulder of said gasket retention groove is formed in said straight portion (1A), and a recession portion (14) retracting in a width direction relatively from said shoulder portion (13) between said main seal portion (11) and the seat seal portion (12) is formed in said corner portion (1B). Accordingly, a partial compression reaction force increase is prevented in the corner portion.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: May 10, 2016
    Assignee: Nippon Mektron, Ltd.
    Inventor: Takahiro Hayashi
  • Publication number: 20160016382
    Abstract: Provided are a layered substrate that has excellent mechanical properties such as a flexural strength or a flexural modulus applicable to a structural material, the variations in those mechanical properties are small, exhibits excellent formability into a complicated shape, and is able to be molded in a short time, and a method for manufacturing the same. A layered substrate fabricated by layering plural sheets of sheet-shaped prepregs containing a reinforcing fiber oriented in one direction and a thermoplastic matrix resin, wherein the prepreg has a slit penetrating from the front surface to the back surface, each slit is provided so as to intersect with each reinforcing fiber only one time.
    Type: Application
    Filed: March 10, 2014
    Publication date: January 21, 2016
    Applicant: MITSUBISHI RAYON CO., LTD.
    Inventors: Takeshi ISHIKAWA, Masao TOMIOKA, Masahiro OSUKA, Yuuji FUJITA, Yokichi KONAMI, Takahiro HAYASHI
  • Publication number: 20150357277
    Abstract: To provide a wiring substrate which can reliably prevent progress of cracking in a solder bump, and which exhibits improved reliability. The wiring substrate 10 of the present invention includes a substrate main body 11, pads 61, and a solder resist 81. The pads 61 are provided on the substrate back surface 13 of the substrate main body, and have surfaces 62 on which solder bumps 84 employed for connection of a motherboard 91 can be formed. The solder resist 81 covers the substrate back surface 13 of the substrate main body, and has openings 82 through which the pads 61 are exposed. A protrusion 71 is formed on a portion of the surface 62 of each pad 61. The height A4 of the end surface 72 of the protrusion 71, as measured from the surface 62 of the pad 61, is smaller than the depth of each opening 82.
    Type: Application
    Filed: December 12, 2013
    Publication date: December 10, 2015
    Inventors: Makoto NAGAI, Seiji MORI, Tatsuya ITO, Takahiro HAYASHI
  • Publication number: 20150334850
    Abstract: A method of manufacturing a wiring substrate according to the present invention includes a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of forming electrically insulative dummy portions separated from the wiring layer on the first insulating layer through patterning of the second insulating layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that upper end portions of the connection terminals protrude from the third insulating layer, and lower end portions of the connection terminals are embedded in the third insulating layer.
    Type: Application
    Filed: May 8, 2015
    Publication date: November 19, 2015
    Inventor: Takahiro HAYASHI
  • Publication number: 20150287724
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20150266004
    Abstract: A catalyst support for purification of exhaust gas includes a porous composite metal oxide, the porous composite metal oxide containing alumina, ceria, and zirconia and having an alumina content ratio of from 5 to 80% by mass, wherein after calcination in the air at 1100° C. for 5 hours, the porous composite metal oxide satisfies a condition such that standard deviations of content ratios (as at % unit) of aluminum, cerium and zirconium elements are each 19 or less with respect to 100 minute areas (with one minute area being 300 nm in length×330 nm in width) of the porous composite metal oxide, the standard deviation being determined by energy dispersive X-ray spectroscopy using a scanning transmission electron microscope equipped with a spherical aberration corrector.
    Type: Application
    Filed: June 20, 2013
    Publication date: September 24, 2015
    Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki Kumatani, Akira Morikawa, Kae Konishi, Kimitoshi Sato, Toshitaka Tanabe, Akihiko Suda, Masahide Miura, Isao Chinzei, Hiromasa Suzuki, Takeshi Nobukawa, Takahiro Hayashi