Patents by Inventor Takahiro Hayashi

Takahiro Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9131621
    Abstract: A wiring substrate includes a layered structure including one or more insulating layers and one or more conductor layers; a plurality of connection terminals formed on the layered structure; a first resin layer formed on the layered structure and having (defining) a plurality of first openings through which the connection terminals are respectively exposed; and a second resin layer formed on the first resin layer and having (defining) a plurality of second openings through which the connection terminals are respectively exposed and which are smaller in opening diameter than the first openings, wherein the second resin layer has, around each of the second openings, an inclined surface which is formed such that the distance between the inclined surface and the layered structure decreases toward the second opening.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: September 8, 2015
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Takahiro Hayashi, Makoto Wakazono, Takeshi Toyoshima, Makoto Nagai, Makoto Origuchi
  • Publication number: 20150216059
    Abstract: To provide a wiring board in which wiring conductors are securely protected by a precise and rigid dam portion formed on an outermost layer of a laminate and that is excellent in connection reliability with a semiconductor chip. A laminate that configures this wiring board includes multiple connection terminal portions and wiring conductors as a conductor layer of the outermost layer. The wiring conductors are arranged at predetermined positions, passing through between multiple connection terminal portions for flip-chip mounting a semiconductor chip. A resin insulating layer of the outermost layer of the laminate has a dam portion and a reinforcement portion. The dam portion covers the wiring conductors. The reinforcement portion is formed, between the wiring conductor and the connection terminal portion that is adjacent to the wiring conductor, lower than a height of the dam portion. The reinforcement portion is concatenated with a side surface of the dam portion.
    Type: Application
    Filed: May 27, 2013
    Publication date: July 30, 2015
    Inventors: Takahiro Hayashi, Makoto Nagai, Tatsuya Ito, Seiji Mori, Makoto Wakazono, Tomohiro Nishida
  • Patent number: 9093283
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: July 28, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20150208501
    Abstract: To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10. The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25. Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction.
    Type: Application
    Filed: May 17, 2013
    Publication date: July 23, 2015
    Inventors: Takahiro Hayashi, Makoto Nagai, Seiji Mori, Tomohiro Nishida, Makoto Wakazono, Tatsuya Ito
  • Publication number: 20150189752
    Abstract: A wiring substrate includes a surface layer having electrical insulation properties and a connection terminal having electrical conduction properties and protruding from the surface layer. The connection terminal includes a base portion, a covering portion and a filling portion. The base portion of the connection terminal is made of an electrically conductive first metal and located adjacent to the surface layer so as to extend through the surface layer and protrude from the surface layer. The covering portion of the connection terminal is made of an electrically conductive second metal having a melting point lower than that of the first metal and located so as to cover the base portion. The filling portion of the connection terminal is made of at least one of the second metal and an alloy containing the first and second metals and located so as to fill a hollow in the base portion.
    Type: Application
    Filed: July 29, 2013
    Publication date: July 2, 2015
    Inventors: Takahiro Hayashi, Seiji Mori, Tatsuya Ito
  • Patent number: 9070825
    Abstract: A thermoelectric conversion module includes a pair of substrates, electrodes formed on the facing surfaces of a pair of the electrodes, a thermoelectric element disposed between the electrodes, and a joining layer that joins the electrodes and the thermoelectric element, in which the thickness of the joining layer is 30 ?m or more, and is formed by sintering paste including metal particles smaller than 100 nm.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: June 30, 2015
    Assignee: Yamaha Corporation
    Inventor: Takahiro Hayashi
  • Publication number: 20150108579
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Application
    Filed: January 7, 2015
    Publication date: April 23, 2015
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20150044470
    Abstract: Provided are a carbon fibre thermoplastic resin prepreg which is a carbon fibre prepreg obtained by impregnating a PAN-based carbon fibre in which the average fibre fineness of a single fibre is 1.0 dtex to 2.4 dtex with a thermoplastic resin, wherein the thermoplastic resin satisfies 20?(FM/FS)?40 (where FM: flexural modulus (MPa) of a resin sheet comprising only the thermoplastic resin, and FS: flexural strength (MPa) of the resin sheet), a method for manufacturing the same, and a carbon fibre composite material employing the carbon fibre prepreg.
    Type: Application
    Filed: March 29, 2013
    Publication date: February 12, 2015
    Applicant: Mitsubishi Rayon Co., Ltd.
    Inventors: Masao Tomioka, Takahiro Hayashi, Saki Fujita, Takeshi Ishikawa, Keigo Yoshida, Takuya Teranishi, Atsushi Takahashi, Kenichi Watanabe, Morio Katagiri, Akinobu Sasaki, Masahiro Oosuka, Hiroshi Tategaki, Takayuki Kobayashi
  • Patent number: 8946770
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20150004327
    Abstract: A conductive member includes a substrate, conductive layers that are provided on both surfaces of the substrate, and contain a conductive fiber having an average minor axis length of 150 nm or less and a matrix, and intermediate layers that are provided between the substrate and the conductive layers, and contain a compound having a functional group capable of interacting with the conductive fiber, and, when surface resistance values of the two conductive layers are represented by A and B respectively, and an A value is equal to or greater than a B value, A/B is in a range of 1.0 to 1.2.
    Type: Application
    Filed: September 18, 2014
    Publication date: January 1, 2015
    Applicant: FUJIFILM Corporation
    Inventors: Kenichi YAMAMOTO, Takahiro HAYASHI, Satoshi KUNIYASU
  • Publication number: 20140318846
    Abstract: A wiring substrate includes a layered structure including one or more insulating layers and one or more conductor layers; a plurality of connection terminals formed on the layered structure; a first resin layer formed on the layered structure and having (defining) a plurality of first openings through which the connection terminals are respectively exposed; and a second resin layer formed on the first resin layer and having (defining) a plurality of second openings through which the connection terminals are respectively exposed and which are smaller in opening diameter than the first openings, wherein the second resin layer has, around each of the second openings, an inclined surface which is formed such that the distance between the inclined surface and the layered structure decreases toward the second opening.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 30, 2014
    Applicant: NGK Spark Plug Co., Ltd.
    Inventors: Takahiro HAYASHI, Makoto WAKAZONO, Takeshi TOYOSHIMA, Makoto NAGAI, Makoto ORIGUCHI
  • Patent number: 8835761
    Abstract: To minimize thermal influence when integrally forming the sealing member on a flexible wiring board, a sealing structure includes a housing, a flexible wiring board inserted therethrough, and a sealing member integrally formed with the flexible wiring board to airtightly seal a gap between the housing and the flexible wiring board, the flexible wiring board includes a base substrate made of an elastic material, an electrically conductive printed wiring layer formed on a surface of the base substrate, and a cover film covering a surface of the printed wiring layer, and the printed wiring layer which crosses the sealing member is formed as a plurality of divided print wiring layers at only a crossing region with the sealing member and its vicinity.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: September 16, 2014
    Assignee: NOK Corporation
    Inventors: Takahiro Hayashi, Makoto Hora, Keiichi Miyajima
  • Patent number: 8817480
    Abstract: In order to provide excellent waterproofness at a low manufacturing cost to a seal structure comprising a housing to which a flexible wiring board (1) is inserted and a seal member (3) integrally formed on said flexible wiring board (1) for hermetically sealing a gap between said housing and said flexible wiring board (1), a whole surface of a sensor member (31) arranged on at least one side of said flexible wiring board (1) is coated by same material as is used in said seal member (3), at a time of integrally forming the seal member (3) on the flexible wiring board (1).
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: August 26, 2014
    Assignee: Nippon Mektron, Ltd.
    Inventor: Takahiro Hayashi
  • Publication number: 20140178587
    Abstract: The present invention is a method for manufacturing a coated material containing a string-shaped filler using a coating device which applies a coating fluid by forming a coating fluid bead in a clearance between a running web wound on a backup roller and a coating head tip, comprising at least an applying step of applying to the web the coating fluid containing a large number of metal nanowires and a drying step of drying a coating layer that has been applied, wherein the clearance is set so as to satisfy h<d?3h, where h indicates the wet film thickness of the coating fluid and d indicates the clearance.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 26, 2014
    Applicant: FUJIFILM Corporation
    Inventors: Satoshi KUNIYASU, Takahiro HAYASHI
  • Patent number: 8737224
    Abstract: Disclosed is a communication method for switching between a first connection state, in which a data unit is transmitted in a first size, and a second connection state, in which a data unit is transmitted in a second size which is larger than the first size. The communication method comprises a step of maintaining the size of a data unit at the first size in a case where there is a transition from the first connection state to the second connection state after there had been a transition from the second connection state to the first connection state.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: May 27, 2014
    Assignee: NTT DoCoMo, Inc.
    Inventors: Takahiro Hayashi, Masafumi Masuda, Hidehiro Ando, Takaaki Sato, Yoshiyuki Yasuda
  • Patent number: 8726484
    Abstract: A waterproofing device is provided for a mobile apparatus, using a thin coaxial cable or an optical cable and capable of being applied to a portable telephone of a bi-directionally openable/closable type. The waterproofing device is adapted to connect housings to each other by a linear member. The waterproofing device is provided with seal members consisting of a rubber-like elastic material and sealing a gap between the housings, and also with a connecting member having opposite ends in the vicinities of which the seal members are integrated. The linear member is passed through the inside of the connecting member to electrically interconnect electronic parts of the housings. The connecting member has a circular tube-like shape consisting of a soft resin material.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: May 20, 2014
    Assignee: Nippon Mektron, Ltd.
    Inventor: Takahiro Hayashi
  • Publication number: 20140124242
    Abstract: A wiring substrate according to the present invention includes a laminate of one or more insulation layers and one or more conductive layers and further includes a plurality of connection terminals formed on the laminate and spaced apart from one another, each having a step formed at the outer periphery of a first main surface opposite a contact surface in contact with the laminate, and a filling member provided in a filling manner between the connection terminals.
    Type: Application
    Filed: May 16, 2012
    Publication date: May 8, 2014
    Applicants: NGK SPARK PLUG CO., LTD., NGK SPARK PLUG CO., LTD.
    Inventors: Tatsuya Ito, Seiji Mori, Takahiro Hayashi, Makoto Wakazono, Tomohiro Nishida
  • Publication number: 20140097007
    Abstract: Embodiments of the present wiring substrate include a stacked body including one or more insulation layers and one or more conductive layers, wherein the wiring substrate has a plurality of connection terminals formed on the stacked body, each connection terminal has a top surface whose area is smaller than that of each of opposite side surfaces thereof, and a filling member provided in a filling manner between the connection terminals. The top surface of each connection terminal has an area larger than that of a portion of each side surfaces portion exposed from the filling member, and a bonding layer containing a solder is formed on the top surface.
    Type: Application
    Filed: September 26, 2013
    Publication date: April 10, 2014
    Applicant: NGK Spark Plug Co., Ltd.
    Inventors: Makoto NAGAI, Seiji MORI, Takahiro HAYASHI, Tatsuya ITO
  • Publication number: 20140069701
    Abstract: A wiring board includes a base layer, a plurality of connection terminals and a surface layer. The base layer is electrically insulative. The plurality of connection terminals are conductive and formed on the base layer. The surface layer is electrically insulative, and fills gaps between the plurality of connection terminals on the base layer. The connection terminals include a base portion made of a conductive first metal and a coating portion made of a conductive second metal that is different from the first metal. The coating portion penetrates the surface layer, and coats the base portion to the base layer.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 13, 2014
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Takahiro HAYASHI, Seiji MORI, Tatsuya ITO
  • Patent number: D736857
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: August 18, 2015
    Assignee: NIPPON CONLUX CO., LTD.
    Inventors: Yasuyuki Kodama, Nobutaka Takefuta, Takahiro Hayashi, Akihiro Nobuhara, Masashi Kondo