Abstract: Electrically functional electronic device including an organic electroluminescence device is protected with a dense protective film, e.g. a silicon oxynitride film, formed on at least one part of the outer surface of the device at a low temperature by ECR plasma sputtering can prevent permeation of moisture, oxygen etc. into the device from the outside.

Abstract: An organic electroluminescent (OEL) element includes a scanning electrode and a signal electrode, which crosses the scanning electrode at right angles, on a substrate. The signal electrodes are formed of N-layer electrodes laminated like steps, where respective layers are insulated from each other. The scanning electrodes are formed on the signal electrodes via an organic thin film layer. As a result, a display area is divided into sections corresponding to laminated numbers, and the divided each section is scanned independently. A duty ratio for driving the OEL element becomes large and less power consumption thus can be expected.

Abstract: An organic electroluminescence element comprising a substrate having provided thereon an anode for injecting holes, a cathode for injecting electrons, and at least one organic compound layer therebetween, wherein the organic compound layer contains at least one compound represented by formula (I), and at least one compound represented by formula (II), (III) or (IV) (definitions of formulas (I) to (IV) are described in the specification).

Abstract: An organic electroluminescence element including a first electrode of a transparent material provided on a substrate of a transparent material. An insulating bulkhead from which a portion of the first electrode is exposed is formed into a thickness so that the insulating bulkhead can be protruded excess to a level of an upper end of the first electrode. An organic thin film is formed on the first electrode and the bulkhead. A second electrode is formed on the organic thin film, wherein the insulating bulkhead comprises an overhang portion and the insulating bulkhead is made of a chromium oxide layer.

Abstract: A power supply voltage detecting circuit detects whether or not a power supply voltage Vcc is a predetermined reference voltage level or more. The power supply voltage detecting circuit generates a self-refresh mode instruct signal &phgr;A to apply the same to a refresh timer when the power supply voltage detecting circuit determine that the power supply voltage Vcc is a predetermined voltage value or less. The refresh timer carries out a clocking operation in response to the self-refresh mode instruct signal &phgr;A to generate a self-refresh request signal &phgr;srf at a predetermined time interval. A semiconductor memory device is implemented which can carry out the self-refresh mode easily without requiring a complicated timing condition of external signals.

Abstract: The invention presents an organic electroluminescence element excellent in long-term durability and reliability, a manufacturing method excellent in mass producibility, and a display device using the organic electroluminescence element. Accordingly, to prevent growth of dark spots in the luminous layer by completely shutting off invasion of moisture or oxygen into an anode or an organic thin film layer, a shield material is adhered to an element by using low melting glass or low melting solder. To fuse the low melting glass or low melting solder used for this purposes, laser or ultrasonic wave is used. The surface of the element is sealed with a protective film in a film thickness of 3 microns to 30 microns, or a protective film composed of two-layer laminate film of insulating compound layer andmetal film. According to these inventions, a highly reliable organic electroluminescence element small in changes in the time course suchas growth of dark sports and lowering of luminance is obtained.

Abstract: An organic thin-film electroluminescent (organic EL) element having an improved luminescent efficiency and improved stability is described, which comprises a substrate and, formed thereover, an anode for injecting holes, a cathode for injecting electrons, and at least one organic-compound layer interposed between the anode and the cathode, wherein the organic-compound layer comprises, for example, any of the following organic compounds.

Abstract: An organic thin-film electroluminescent display device comprising a substrate, hole injection electrodes, an organic thin film layer, electron injection electrodes, an electrode-driving IC for driving the electron injection electrodes and the electron injection electrodes and lead wires for connecting the hole injection electrodes and the electron injection electrodes to the electrode-driving IC. The lead wires each include a lead underlayer made of the same material of the hole injection electrode and a lead electroconductive layer formed on the lead underlayer and having a higher electroconductivity than that of the lead underlayer and or the electron injection electrodes each may include an underlayer for the electron injection electrode and an electroconductive layer for the electron injection electrode formed on the underlayer for the electron injection electrode and having a higher electroconductivity than that of the underlayer for the electron.

Abstract: A dynamic random access memory includes an improved redundant use detection circuit, a redundant fuse circuit for programming a defective row, and a redundant enable circuit for enabling the redundant fuse circuit. Redundant use detection circuit includes a switching element responsive to a redundant use signal from the redundant enable circuit for conducting. High voltage is applied through an external terminal in a redundant use detection mode, and use of a redundant circuit is detected by the presence of current flowing into the redundant use detection circuit. Since a fuse element is not necessary in the redundant use detection circuit, integration density is further improved, thus permitting easy detection of use of a redundant circuit as well.

Abstract: A semiconductor memory device comprises eight memory arrays arranged in one column. A peripheral circuit is arranged in the central portion of the eight memory arrays, two column decoders being arranged with the peripheral circuit interposed therebetween. Each of the eight memory arrays is provided with a row decoder. A plurality of first column selecting lines are provided so as to cross the three memory arrays arranged on one side of the peripheral circuit from the column decoder. In addition, a plurality of second column selecting lines are provided so as to intersect with the three memory arrays arranged on the other side of the peripheral circuit from the column decoder.

Abstract: In a DRAM having two I/O lines commonly provided for reading and writing data and an amplifying circuit for providing a read data signal by amplifying potential difference between the two I/O lines, a potential difference control circuit 8 is provided which includes detecting circuits each having a parallel connected circuit of two MOS transistors each being diode-connected, and a switch circuit which is rendered conductive only at data reading.Since the maximum value of the potential difference between the two I/O lines during data reading is controlled to several times that of the threshold voltage of a MOS transistor, the time necessary for equalizing the I/O lines at data reading can be reduced. Consequently, the speed of change of the output potential of the amplifying circuit changing to the potential corresponding to the data stored in the memory cell MC is increased, and therefore the access time is reduced.

Abstract: A dynamic type semiconductor memory device includes m memory blocks each having a plurality of memory cells, and a plurality of sense amplifier groups associated with the respective memory blocks. Each sense amplifier group senses and amplifies data of a selected memory cell in the related memory block. The memory device further includes a circuit for generating a refresh instruction detecting signal in response to an externally applied refresh mode indicating signal, and circuitry responsive to a block designating signal and the refresh instruction detecting signal for activating each of the sense amplifier groups in such a manner that only start timings for the sensing operations of the sense amplifier groups related to the designated memory blocks may differ from each other.

Abstract: A pen nib preferably for use in a high speed writing, having a coaxial capillary passage for ink. The coaxial passage extends axially in the nib body, and has, in a cross-sectional view, a coaxial portion, a plurality of outer portions and intermediate connecting portions between the coaxial portion and respective outer portions. The coaxial passage partially opens axially at peripheral openings formed in a round or sharped head of the nib, that is the coaxial portion and intermediate portions are all closed axially at the head, and the outer portions are open axially at the peripheral openings formed such that they are arranged at a top surface of the head around the center thereof. The intermediate passage portions may be open radially at the peripheral openings. The nib is made of hard and wear material such as metal, ceramic or thermosetting resin by an injection molding with a subsequent heat treatment.

Abstract: A dynamic-type semiconductor memory device has a test mode of simultaneously carrying out functional testing on a plurality of bits of memory cells. In data writing in the test mode, data inverted from the write-in data is written in at least a 1-bit memory cell out of the plurality of bits of memory cells selected simultaneously, and the same data as the write-in data is written in the remaining memory cells. In data reading in the test mode, the data of those of the memory cells selected simultaneously, in which the inverted data is written are inverted and read, while the data of the remaining memory cells are read as they are. Logic processing is carried out on the read-out data of the plurality of bits, so that a logic value indicating acceptability of the semiconductor memory device is output, depending on a result of determination as to whether or not the read-out data is the same as each other.

Abstract: A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.

Abstract: A semiconductor memory device comprises eight memory arrays (b 10a, 10b) arranged in one column. A peripheral circuit (60) is arranged in the central portion of the eight memory arrays (10a, 10b), two column decoders (51, 52) being arranged with the peripheral circuit (60) interposed therebetween. Each of the eight memory arrays (10a, 10b) is provided with a row decoder (20). A plurality of first column selecting lines (CL1) are provided so as to cross the three memory arrays (10a, 10b) arranged on one side of the peripheral circuit (60) from the column decoder (51). In addition, a plurality of second column selecting lines (CL2) are provided so as to intersect with the three memory arrays (10a, 10b) arranged on the other side of the peripheral circuit (60) from the column decoder (52).

Abstract: A memory cell array (10) is divided into four blocks. Each block comprises a memory cell array block (10aand a memory cell array block (10b). A sense amplifier block (20) is disposed between the memory cell array blocks (10a) and (10b). Each sense amplifier block (20) is connected to the memory cell array blocks (10a) and (10b) via switching circuits (80a, 80b), respectively. Four decoders (51) are provided corresponding to the four blocks. The four decoders (51) are commonly provided with a driver (52) generating a high level driving signal. Each decoder (51) is responsive to an address signal for supplying a driving signal from the driver (52) to either one of the switching circuits (80a, 80b) and for applying a ground potential to the other one of the circuits. Accordingly, the sense amplifier block (20) is connected to either one of the memory cell array blocks (10a, 10b ).

Abstract: An input signal is inverted by a CMOS inverter and provided for an output signal line. The CMOS inverter is provided between a power supply and a ground, and its node on the side of the power supply is charged all the time to prevent the potential thereof from being lowered. An output signal provided for the output signal line is delayed by a delay circuit to be applied to a boosting capacitor. The potential of the node is further boosted by this boosting capacitor. Consequently, the potential of the output signal is also boosted. When the potential of the node is raised higher than a supply voltage, an N channel MOSFET for charging is turned off to prevent a reverse flow of a charge.

Abstract: In a dynamic random access memory (DRAM), there is provided a refresh decision circuit which detects the external designation of a self refresh mode, in addition to a CAS before RAS refresh mode, by RAS and CAS signals. By detecting a time period of one cycle of the RAS, the self refresh mode is determined. As a result, the timing of change of the RAS signal is less restricted.

Abstract: In a dynamic random access memory (DRAM), there is provided a refresh decision circuit which detects the external designation of a self refresh mode, in addition to a CAS before RAS refresh mode, by RAS and CAS signals. By detecting a time period of one cycle of the RAS, the self refresh mode is determined. As a result, the timing of change of the RAS signal is less restricted.