Abstract: According to one embodiment, a display device includes a first line which is arranged across a display portion, and includes a first end portion and a second end portion located at a non-display portion such that the display portion is located between the first and second end portions, a first switch electrically connected to the first end portion, a second switch electrically connected to the second end portion, a first terminal electrically connected to the first end portion via the first switch, and a second terminal electrically connected to the second end portion via the second switch.

Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Abstract: A circuit block of a driving circuit of a display device includes a first transistor that has a gate being connected to a first node having an active potential during an output period, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period, and controls electrical conduction between the first node and an inactive potential line, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line applied with a first period signal having an active potential at the time of termination of the output period.

Abstract: The present invention realizes a bright image display by enhancing a numerical aperture of pixels. At least a portion of a pixel electrode is overlapped to a thin film transistor by way of a first insulation film, the pixel electrode is connected to an output electrode of the thin film transistor via a contact hole which is formed in the first insulation film, the counter electrode is arranged above the pixel electrode by way of a second insulation film in a state that the counter electrode is overlapped to the pixel electrode, the counter electrode is formed at a position avoiding the contact hole formed in the first insulation film as viewed in a plan view, and at least a portion of the counter electrode is overlapped to the thin film transistor.

Abstract: A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Abstract: A liquid crystal display device includes a thin film transistor substrate, a counter substrate that faces the thin film transistor substrate, a liquid crystal composition that is arranged between the thin film transistor substrate and the counter substrate, an oriented film that arranges orientation of the liquid crystal composition contacting with the thin film transistor substrate, a seal material that seals the liquid crystal composition between the two substrates, and a driver circuit. The driver circuit has a light transmission area that is formed inside of the driver circuit, and is higher in light transmittance than an area in which a non-transparent conductive film forming the driver circuit is formed, and a high sealing property area in which the seal material and an insulating film come into direct contact with each other between the light transmission area and an outer edge of the thin film transistor substrate.

Abstract: A circuit block of a driving circuit of a display device includes a first transistor that has a gate being connected to a first node having an active potential during an output period, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period, and controls electrical conduction between the first node and an inactive potential line, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line applied with a first period signal having an active potential at the time of termination of the output period.

Abstract: A three-dimensional display device prevents a barrier wire breakage failure and includes a parallax barrier panel resistant to static electricity. The 3D display device has a liquid crystal parallax barrier panel disposed over a display panel. The parallax barrier panel has a first substrate having an electrode formed flat thereon and a second substrate having a display area, the first substrate and the second substrate having liquid crystal sandwiched therebetween. The second substrate has barrier electrodes extending in a first direction and arrayed at a first pitch in a second direction, has a first bus electrode extending in the second direction outside the display area along a first side thereof, and has a second bus electrode extending in the second direction outside the display area along a second side thereof opposite to the first side. The barrier electrodes are connected to the first and the second bus electrodes.

Abstract: A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

Abstract: A liquid crystal display device includes a thin film transistor substrate, a counter substrate that faces the thin film transistor substrate, a liquid crystal composition that is arranged between the thin film transistor substrate and the counter substrate, an oriented film that arranges orientation of the liquid crystal composition contacting with the thin film transistor substrate, a seal material that seals the liquid crystal composition between the two substrates, and a driver circuit. The driver circuit has a light transmission area that is formed inside of the driver circuit, and is higher in light transmittance than an area in which a non-transparent conductive film forming the driver circuit is formed, and a high sealing property area in which the seal material and an insulating film come into direct contact with each other between the light transmission area and an outer edge of the thin film transistor substrate.

Abstract: A parallax barrier panel including a first substrate having a flat electrode, and a second substrate, the liquid crystal sandwiched therebetween. The second substrate has first barrier electrodes extending in a first direction and arrayed at a first pitch in a second direction, and has second barrier electrodes, the first and the second harrier electrodes having an interlayer insulating film interposed therebetween. Gaps between the first barrier electrodes are blocked by the second barrier electrodes when viewed in a plan view. Each of the first barrier electrodes is paired with one of the second barrier electrodes. Bus electrodes extend outside the display area along a side thereof. The first barrier electrodes are connected to the bus electrodes via first through holes formed in the interlayer insulating film. The second barrier electrodes are connected to the first barrier electrodes via second through holes formed in the interlay insulating film.

Abstract: A column for defining the interval between a TFT substrate and an opposed substrate is formed at a crossing point between a drain line and a scanning line. At the crossing point where the column is formed, the drain line is formed to have a wider width to prevent light leakage. Further, at the crossing point where the column is formed, the scanning line is formed to have a narrower width to prevent increase of capacitance between the drain line and the scanning line. The column is formed at a crossing point corresponding to a specific color, e.g., a blue pixel B, so that a difference in transmittance and in characteristic of thin film transistors due to formation of the column is initially compensated.

Abstract: A column for defining the interval between a TFT substrate and an opposed substrate is formed at a crossing point between a drain line and a scanning line. At the crossing point where the column is formed, the drain line is formed to have a wider width to prevent light leakage. Further, at the crossing point where the column is formed, the scanning line is formed to have a narrower width to prevent increase of capacitance between the drain line and the scanning line. The column is formed at a crossing point corresponding to a specific color, e.g., a blue pixel B, so that a difference in transmittance and in characteristic of thin film transistors due to formation of the column is initially compensated.

Abstract: Second barrier electrodes are arranged under first barrier electrodes so as to fill gaps between the first barrier electrodes, while an insulating layer is located between the first barrier electrodes and the second barrier electrodes. The number of first barrier electrodes and the number of second barrier electrodes in each barrier pitch are 6 or more. The positions of the barriers formed by the first barrier electrodes and the second barrier electrodes are controlled by the reception of a signal representing detected positions of the eyes of a viewer. If pitches of the first barrier electrodes are defined as BE, and the widths of regions in which the first barrier electrodes are overlapped with the second barrier electrodes are defined as BA, a ratio BA/BE of the widths BA to the pitches BE are 0.3 or smaller. This configuration can suppress the occurrence of moire.

Abstract: A liquid crystal display device includes first and second substrates with liquid crystal sandwiched therebetween. A first blue, a red, a green, and a second blue color filters are disposed between the first substrate and the second substrate, and arranged in a first direction. First to third light blocking films are respectively disposed between the first blue and the red color filters, between the red and the green color filters, and between the green and the second blue color filters. A distance Lr between a first central line of a part of the first light blocking film and a second central line of a width the second light blocking film is larger than a distance Lg between the second central line and a third central line of a width of the third blocking film.

Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Abstract: A gate signal line drive circuit whose power consumption is reduced, is provided. In the gate signal line drive circuit having plural basic circuits outputting respective gate signals, each basic circuit includes a high voltage application switching element to which a first basic clock signal having high voltage in a signal high period is input, a low voltage application switching element that turns on at timing starting a signal low period, and outputs a low voltage, and a first low voltage application on control element having an input terminal to which a second basic clock signal subsequent to the first basic clock signal is input, and which turns on according to the signal high period, and outputs the voltage of the second basic clock signal to the control terminal of the low voltage application switching element.

Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Abstract: A liquid crystal display device having an alignment layer stopper which is formed external to a display area to suppress the generation of an electric field between signal lines and the alignment layer stopper, wherein the alignment layer stopper includes a second conductive layer SP formed above the first substrate when the alignment layer stopper is formed by coating and a first conductive layer SH formed below the second conductive layer SP through an insulating film and arranged in such a manner that its marginal parts in the longitudinal direction of the second conductive layer SP are exposed when viewed from the plane direction from the second conductive layer SP, and the first conductive layer SH is formed in a thin film layer between signal lines arranged in the side parts of the display area and the second conductive layer SP.