Abstract: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.

Abstract: A determining method executed by a processor includes obtaining distance information that indicates a distance between monitoring apparatuses disposed to encompass a given area in which wireless communications apparatuses are scattered; causing a wireless signal to be transmitted and received between the monitoring apparatuses by multi-hop communication among the wireless communications apparatuses; calculating an estimated distance between the monitoring apparatuses, based on a hop count of the wireless signal multi-hop communicated among the monitoring apparatuses; and making a determination concerning a vacant area in which none of the wireless communications apparatuses is present, based on a result of comparison of the distance indicated by the obtained distance information and the calculated estimated distance.

Abstract: In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal.

Abstract: An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device.

Abstract: A sensor node detects an occurrence of sensing and judges whether data processing corresponding to the sensing will finish before an occurrence of sensing subsequent to the sensing, based on a time interval when the occurrence of the sensing is detected. When determining that the data processing will finish, the sensor node executes the data processing and transmits the execution result of the data processing to a first apparatus directly communicable with the sensor node. When determining that the data processing will not finish, the sensor node transmits, to the first apparatus, request information causing the first apparatus to execute the data processing and to transmit the execution result of the data processing to a second communication apparatus directly communicable with the first apparatus.

Abstract: An anti-vibration rubber member includes: a rubber elastic body that is made of a self-lubricating rubber containing an elastomer and a bleeding lubricant; a coating film that covers at least a portion of a sliding inner surface that is among a surface of the rubber elastic body and disposed on an inner side of the sliding surface, contains a resin having a mercapto group, is deformable to follow up deformation of the rubber elastic body, and is formed with a plurality of minute holes capable of reserving the bleeding lubricant which has oozed out of the rubber elastic body; and a lubricating film that covers at least a portion of a surface of the coating film, is formed to include the bleeding lubricant penetrating the coating film from the rubber elastic body and oozing onto the surface of the coating film, and forms at least a portion of the sliding surface.

Abstract: A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the cores in the multicore processor; and restoring, when the suspend instruction is detected, data stored in a volatile memory accessed by a core receiving the suspend instruction, the data being restored in a shared memory accessed by the cores in operation and based on parity data stored in the volatile memories accessed by the cores in operation other than the core receiving the suspend instruction.

Abstract: A data processing apparatus that is installed in plural in an installation area and processes data of each installation site, includes a processor that based on a combination of identification information included in calibration information respectively transmitted by calibration nodes and self-identification generation information that is included in the calibration information and for identifying the data processing apparatus among the plural data processing apparatuses, generates self-identification information; a memory device that retains the self-identification information; and a wireless communications circuit that receives the calibration information from the calibration nodes and performs transmission and reception of the data with an adjacent data processing apparatus provided in the installation area.

Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.

Abstract: A communication device has: a sensor configured to output sensing data; a count signal communication part configured to count a count signal received from a control device directly or via another communication device and transmit the counted count signal and to store a value of the received count signal; and a data communication part configured to transmit the sensing data outputted by the sensor or the sensing data received from another communication device, in correspondence with the stored value of the count signal.

Abstract: A position estimation apparatus acquires, for base devices, the number of hops from a target sensor node to a base device. The position estimation apparatus calculates, for each base device, a distribution of estimated distances corresponding to the total hops, based on the number of hops and a distribution of estimated distances stored in a storage device. The position estimation apparatus calculates, for each base device, a distribution of estimated positions within a given region, based on the distribution of estimated distances, information concerning a range of the given region, and information concerning a position of the base device. The position estimation apparatus calculates an index that indicates a probability of a position of the target sensor node within the given region, based on the sum of distributions of estimated positions concerning the base stations.

Abstract: A first communication apparatus includes a first central processing core; and a first memory. The first communication apparatus executes load distribution based on a first load amount of the first communication apparatus and a second load amount of a second communication apparatus that includes a second central processing core and a second memory. The first communication apparatus executes first load distribution when the first communication apparatus and the second communication apparatus perform wireless communication. The first communication apparatus executes second load distribution when the first communication apparatus and the second communication apparatus perform wired communication.

Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Abstract: A memory stores data generated by a processor and a transferring unit burst transfers the data from the memory unit to a processing unit. Based on an access capability of the processor when accessing the memory, a prescribed value for a burst width and information concerning the time that the processing unit consumes to process the data are set in advance at the data transferring apparatus. When the transferring unit performs data transfer, the time allowed for data transfer is calculated based on the information concerning the time that the processing unit consumes to process the data, and the burst width is determined as a value greater than or equal to the prescribed value for the burst width and is as close as possible to the prescribed value for the burst width within a range in which data transfer can be finished within the allowed time.

Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.

Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.

Abstract: A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request.

Abstract: A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers.

Abstract: A data processing apparatus includes a storage unit configured to store plural data processing programs and a corresponding error processing program for when an error occurs with a first data processing program; and a processor configured to record to memory before executing the first data processing program, information of the error processing program that corresponds to the first data processing program; update and record in the memory after the first data processing program ends, information of a second data processing program scheduled to be executed next; and switch to any one among the first data processing program that corresponds to information recorded in the memory and the error processing program, when program processing is started next.

Abstract: A coprocessor stores to local memory, a driver execution start time, for each execution start of drivers. If a CPU call process is executed during the execution of driver A, the coprocessor calculates the difference of the execution start time and the current time, for drivers B and C. Taking driver C as an example, the coprocessor adds to the difference calculated for the driver C, a processing time required for the CPU call process of driver A and a processing time required for a normal process of driver B. The coprocessor determines whether respective addition results for driver C comply with respective time constraints. If it is determined that an addition result for the driver C cannot comply with the time constraint, and the coprocessor sends an execution request for driver C to another coprocessor.