Abstract: A detecting apparatus includes processors configured to access sensors; select from among the sensors, a sensor that has not been selected by any processor, acquire data from the selected sensor, and release selection of the sensor when data acquisition has been completed; execute processing for the sensor, based on the acquired data; set the sensor to an execution state during execution of the processing for the sensor, and set the sensor to an execution completed state when the execution of the processing for the sensor has ended; copy from a processor that has set the sensor to the execution state, the data acquired from the sensor by the processor, upon determining the sensor to be in the execution state, without executing the data acquisition; and execute the processing for the sensor, based on the copied data.

Abstract: A data processing apparatus includes a processor configured to receive an interrupt request that is a trigger for execution of an interrupt process executed by the processor; store the received interrupt request to a recording area; calculate based on a time when the interrupt request is received and particular time information read from the recording area, a predicted time when a subsequent interrupt request is to be received; detect a thread to be executed by the processor, among executable threads of the processor; judge based on the calculated predicted time and a current time, whether there is a possibility of the interrupt process being executed while the detected thread is under execution; decide based on a judgment result, whether to execute the detected thread on the processor; and execute the detected thread on the processor, based on a decision result.

Abstract: A three-chip camera apparatus includes: a color separation prism which includes an incident surface perpendicular to an optical axis, a first emission surface parallel to the incident surface, a second emission surface inclined at a first inclination angle with respect to the optical axis, and a third emission surface inclined at a second inclination angle greater than the first inclination angle; a first imaging device which is disposed in parallel to the first emission surface; a second imaging device which is disposed in parallel to the second emission surface; and a third imaging device which is disposed in parallel to the third emission surface.

Abstract: A bearing steel includes, as a metallographic structure, inclusions which contain complex oxysulfides including Rare Earth Metal, Ca, O, S, and Al, TiN, MnS, Al2O3, and complex oxides including Al and Ca, wherein, a number fraction of the complex oxysulfides in a total number of the inclusions is 50% to less than 100% and a number of complex oxysulfides having a major axis of 5 ?m or more is 0.001 pieces to 2 pieces in an observed section of 1 mm2, and a number of TiN existing independently from the complex oxysulfides and having a major axis of 5 ?m or more is 0.001 pieces to less than 1.0 piece in an observed section of 1 mm2.

Abstract: A system includes a CPU; an accelerator; a comparing unit that compares a first value that is based on a first processing time period elapsing until the CPU completes a first process and a second processing time period elapsing until the accelerator completes the first process, and a second value that is based on a state of use of a battery driving the CPU and the accelerator; and a selecting unit that selects any one among the CPU and the accelerator, based on a result of comparison by the comparing unit.

Abstract: A communication method includes performing, by a processor, digital processing for radio communication by multiple communication schemes; combining based on an actual communication state and within a processing capability of the processor, one or more among the communication schemes; and performing concurrent communication.

Abstract: An electronic computer includes a processor that executes a thread and an interrupt handler, and monitors load of the processor; and an interrupt controller that is configured to determine a notification timing for an interrupt request to call the interrupt handler, the notification timing being determined based on the load and an effect of execution of the interrupt handler on user performance of the thread under execution by the processor; and notify the processor of the interrupt request, based on the notification timing. When the load is higher than a threshold, the interrupt controller sets the notification timing for an interrupt request that does not affect the user performance, to be later than the notification timing for an interrupt request that affects the user performance. Based on notification of the interrupt request, the processor calls and executes the interrupt handler that corresponds to the interrupt request.

Abstract: A power control apparatus includes a processor configured to collect first information related to operation of a performing unit configured to perform data processing and information related to operation of a bus configured to transfer data; determine an operating frequency and an operating voltage for the performing unit, based on the collected information; estimate based on the collected information, a period elapsing until the performing unit suspends operation and a period elapsing until the bus suspends operation; derive a discriminant that obtains a difference of total power consumption and power consumption pre-switching; and execute a switching of an operating frequency and an operating voltage of the performing unit, based on a value of the discriminant.

Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.

Abstract: An interrupt monitoring apparatus includes a storage that stores a given threshold that corresponds to an external interrupt notification; a measuring circuit that measures time that elapses from a time when the external interrupt notification is received until a time when dispatch notification is received from a CPU; a comparing circuit that compares the given threshold and the time measured by the measuring circuit; and an output circuit that outputs to the CPU, a comparison result obtained by the comparing circuit.

Abstract: A data processing method is executed by a first data processing apparatus, and includes setting based on a size of data that is for executing a predetermined function, a first division number for dividing the data; producing groups of a second division number, each including N (a positive integer) elements by dividing the first division number; assigning a plurality of data processing apparatuses each capable of communicating with the first data processing apparatus, to the groups of the second division number; and assigning sub-data formed by dividing the data by the first division number, to the groups of the second division number.

Abstract: A scheduling method includes determining whether priority of an application to be activated is of a given priority, the determining being performed by a first data processing apparatus that is included in a first group having at least one data processing apparatus; transferring to a second data processing apparatus that is included in any one among a second group and the first group, a predetermined function of the first data processing apparatus so as to execute the application by the first data processing apparatus, the transferring being performed when the priority of the application is of the given priority, and the first and the second groups being among a plurality of groups that each includes at least one data processing apparatus; and placing the application in an execution queue of the first data processing apparatus, when the priority of the application is not the given priority.

Abstract: A data processing system includes multiple data processing apparatuses; a peripheral apparatus; memory that is shared by the data processing apparatuses and the peripheral apparatus; peripheral memory provided corresponding to the peripheral apparatus; and a memory managing unit that secures in any one among the memory and the peripheral memory, an area for a thread that is based on thread information, the area being secured based on the thread information that is read out from a heap area that sequentially stores the thread information that is executed at any one among the data processing apparatuses and the peripheral apparatus.

Abstract: A scheduling system includes a processor that is configured to assign a process to at least one data processing system among plural data processing systems, based on an execution request for the process; estimate time consumed for completion of a first process, when the process is the first process; and append specific information to the first process, based on the estimated time.

Abstract: A data processing system includes an interrupt controller that counts, as an interrupt processing execution count, executions of interrupt processing by threads executed by data processing devices; and a processor that is configured to select one scheduling method from among a plurality of scheduling methods, based on the interrupt processing execution count.

Abstract: An assignment method executed by a given core of a multi-core processor includes identifying for each core, the number of storage areas to be used by a given thread and the number of storage areas used by threads already assigned; detecting for each core, a highest value from the number of storage areas used by the threads already assigned; determining whether a sum of a greater value of the detected highest value of a core selected as a candidate assignment destination and the number of storage areas to be used by the given thread, and the detected highest value of the cores excluding the selected core, is at most the number of storage areas of the shared resource; and assigning the given thread to the selected core, when the sum is at most the number of storage areas of the shared resource.

Abstract: A multi-core processor system includes a multi-core processor that has plural core groups; and a storage device that stores a constraint on execution time for each application. A first identified core of the multi-core processor is configured to identify a constraint on execution time of a given application that is among the applications and for which an invocation instruction is received; determine whether the identified constraint meets a performance drop condition; assign the given application to a predetermined core of the multi-core processor, upon determining that the identified constraint meets the performance drop condition; and notify a second identified core of a core group among the core groups, of an assignment instruction for the given application, upon determining that the identified constraint does not meet the performance drop condition.

Abstract: A data processing method that is executed by a data processing system includes determining whether an application whose startup is requested by a first data processing apparatus among a plurality of data processing apparatuses, belongs to a predetermined group; determining whether a second data processing apparatus among the data processing apparatuses has started up the application, when the application belongs to the predetermined group; and aborting startup of the application by the first data processing apparatus, when the second data processing apparatus has started up the application.

Abstract: A control terminal has access to a storage apparatus storing a first processing period for execution of an application by sequential processing and a second processing period for execution of the application by parallel processing; and includes a processor configured to transmit an execution request for the application to a request terminal upon accepting a startup instruction for the application; receive a response to the execution request; determine whether a sum of the second processing period and a difference of a reception time of the response and a transmission time of the execution request, is at least the first processing period; and execute the application by sequential processing by the control terminal when the sum is at least equal to the first processing period, and execute the application by parallel processing using the control terminal and the request terminal when the sum is less than the first processing period.

Abstract: A data processing method that is executed by a processor includes determining based on a size of an available area of a first memory whether first data of a first thread executed by a first data processing apparatus among a plurality of data processing apparatuses is transferable to a first memory; transferring second data that is of a second thread and stored in the first memory to second memory, when at the determining, the first data is determined to not be transferrable; and transferring the first data to the first memory.