Abstract: In an analog-to-digital converter circuit, a sum output unit calculates the sum of an n-bit data value outputted from a first output unit and an (n + 1)-bit data value outputted from a second output unit to accordingly obtain the calculated sum as a digital data value. A second calculator of the second output unit calculates the sum of a sign bit of a third digital data value as a most significant bit thereof and a second significant bit of the third digital data value. The combines a bit selected from the calculated sum with the third digital data value from which the sign bit has been eliminated to accordingly generate, as the (n + 1)-bit data value, a new digital data value whose most significant bit is the bit selected from the calculated sum.

Abstract: In an analog-to-digital converter, primary latches respectively latch an output of a corresponding one of delay units at respective sample times of different first clocks. The primary latches include at least first and second primary latches, and secondary latches include at least first and second secondary latches respectively corresponding to the at least first and second primary latches. Each of the at least first and second secondary latches is configured to latch, at a sample time of a common second clock, an output of a corresponding one of the at least first and second primary latches. The common second clock is based on at least one of the first clocks.

Abstract: An A/D converter circuit that converts analog information to numerical data is provided with a pulse delay circuit and an output unit. A sampling period is set so that a relationship between the sampling period and a circulation period of a pulse signal passing through a ring delay circuit satisfies a relational expression Trdl×n<Ts ?Trdl×(n+1). In the relational expression, Ts is the sampling period, Trdl is the circulation period in which the pulse signal circulates through the pulse delay circuit, and “n” is an integer equal to or greater than 0.

Abstract: An A/D conversion circuit converts an analog signal into numerical data. The A/D conversion circuit includes: a pulse delay circuit that includes an odd number of delay units connected in series, and inverting and delaying a pulse signal, and that changes the numeral number of the delay units which the pulse signal passes through in accordance with a value of the analog signal; latch circuits that synchronize the pulse signal with sampling clocks, and latch the pulse signal; encoders that set a position of the pulse signal to the numerical data by circulating encode values periodically set in order from an initial value to a final value to synchronously sample the encode values; subtractors that calculate each of differences between a previous value and a current value; and an adder that adds subtraction results. The encode values are set to be shifted between at least two encoders.

Abstract: An A-D conversion circuit configured to convert an analog input signal into numerical data using a pulse delay circuit includes pulse position digitizing units, a clock generation circuit, and a processing unit. The clock generation circuit includes inverters each including one or more n-channel transistors and one or more p-channel transistors. The inverters differ from each other in a number ratio of the number of n-channel transistors connected in a common-gate parallel-connected manner and the number of p-channel transistors connected in a common-gate parallel-connected manner.

Abstract: An A/D conversion circuit converts an analog signal into numerical data. The A/D conversion circuit includes: a pulse delay circuit that includes an odd number of delay units connected in series, and inverting and delaying a pulse signal, and that changes the numeral number of the delay units which the pulse signal passes through in accordance with a value of the analog signal; latch circuits that synchronize the pulse signal with sampling clocks, and latch the pulse signal; encoders that set a position of the pulse signal to the numerical data by circulating encode values periodically set in order from an initial value to a final value to synchronously sample the encode values; subtractors that calculate each of differences between a previous value and a current value; and an adder that adds subtraction results. The encode values are set to be shifted between at least two encoders.

Abstract: A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes (2n?(2m?1)) first delay units connected in series, and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes (2n+(2m?1)) second delay units connected in series, and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and n?m. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.

Abstract: An A/D converter circuit that converts analog information to numerical data is provided with a pulse delay circuit and an output unit. A sampling period is set so that a relationship between the sampling period and a circulation period of a pulse signal passing through a ring delay circuit satisfies a relational expression Trdl×n<Ts ?Trdl×(n+1). In the relational expression, Ts is the sampling period, Trdl is the circulation period in which the pulse signal circulates through the pulse delay circuit, and “n” is an integer equal to or greater than 0.

Abstract: An A-D conversion circuit configured to convert an analog input signal into numerical data using a pulse delay circuit includes pulse position digitizing units, a clock generation circuit, and a processing unit. The clock generation circuit includes inverters each including one or more n-channel transistors and one or more p-channel transistors. The inverters differ from each other in a number ratio of the number of n-channel transistors connected in a common-gate parallel-connected manner and the number of p-channel transistors connected in a common-gate parallel-connected manner.

Abstract: A gyro sensor apparatus includes a driving section that supplies a driving signal, which is for vibrating a sensing element of a vibration-type gyro sensor in a drive axis direction, to the sensing element, and a processing unit that receives a first vibration signal having an amplitude proportional to a driving vibration amplitude, which is an amplitude of vibration in the drive axis direction of the sensing element and a second vibration signal having an amplitude proportional to Coriolis force generated in the sensing element due to an angular velocity of the sensing element. The processing unit is configured to calculate a ratio of Coriolis force to the driving vibration amplitude based on the first vibration signal and the second vibration signal and output a result of the calculation as a result of detection of the angular velocity of the sensing element.

Abstract: A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes first delay units connected in series by (2n-(2m?1)), and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes second delay units connected in series by (2n+(2m?1)), and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and n?m. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.

Abstract: A first encoding part encodes a reference timing determined by a reference clock by using a delay line. A second encoding part encodes a measurement start timing and a measurement end timing of a measurement period determined by a measurement signal to be measured by also using the delay line. A count part counts the reference clocks included in the measurement period. A fraction calculation part calculates a start fraction number indicating a time difference from the measurement start timing and an immediately-following reference timing and an end fraction number indicating a time difference from the measurement end timing to an immediately-following reference timing, based on the encoding result. The fraction calculation part then calculates a fraction data indicating a difference between the measurement period and a product of the period of the reference timing and the count value of the count part.

Abstract: A gyro sensor apparatus includes a driving section that supplies a driving signal, which is for vibrating a sensing element of a vibration-type gyro sensor in a drive axis direction, to the sensing element, and a processing unit that receives a first vibration signal having an amplitude proportional to a driving vibration amplitude, which is an amplitude of vibration in the drive axis direction of the sensing element and a second vibration signal having an amplitude proportional to Coriolis force generated in the sensing element due to an angular velocity of the sensing element. The processing unit is configured to calculate a ratio of Coriolis force to the driving vibration amplitude based on the first vibration signal and the second vibration signal and output a result of the calculation as a result of detection of the angular velocity of the sensing element.

Abstract: A digital control oscillator circuit includes: a ring oscillator having delay elements delaying a pulse signal; a counter circuit counting the circulation number of the pulse signal; a rough period generation unit acquiring a period setting value as a magnification ratio for a reference clock, and counting the reference clock using an integer part of the ratio to generate a rough period timing; a fraction conversion unit converting a decimal point part of the ratio into the number of the elements passed by the pulse signal to generate a fraction; and an output processing unit selecting a timing when outputs of the ring oscillator and the counter circuit become values corresponding to the fraction as an output timing when a time corresponding to the fraction has passed after the rough period timing, and generating an output signal oscillating at a period represented by the period setting value according to the output timing.

Abstract: A gyro sensor includes a vibrator and a drive circuit. A PWM drive signal is applied to a pair of electrodes of the vibrator. The drive circuit outputs a high level signal and a low level signal to the electrodes as the PWM drive signal. The high level signal and the low level signal have potentials higher and lower than that of the reference signal, respectively. The drive circuit outputs the high level signal to one of the pair of electrodes and the low level signal to the other of the pair of electrodes.

Abstract: In a gyro sensor, a TDC detects a magnitude of vibration of a vibrator. A drive circuit (excluding the TDC) determines a duty ratio of a PWM drive signal in accordance with the magnitude of vibration so that the magnitude of vibration becomes a predetermined magnitude and outputs the PWM drive signal having the determined duty ratio. The drive circuit (excluding the TDC) includes a control circuit and a DCO. The control circuit measures time corresponding to the control value by using a gate delay time, generates the PWM drive signal having a pulse width corresponding to the control value and outputs the PWM drive signal.

Abstract: A demodulation device for demodulating a base signal from a composite signal, which is composed of a carrier wave and a sensor modulation signal of the base signal. The demodulation device determines a difference between the composite signal of a former-half period and the composite signal of a latter-half period to be a pre-correction base signal. The former-half period is a one-half period of a sampling period starting at one of a local maximum and a local minimum of the carrier wave. The latter-half period follows the former-half period. The demodulation device determines a reference level from the composite signal and determines a signal level of a post-correction base signal based on a ratio between a signal level of the pre-correction base signal and the reference level.

Abstract: A digital control oscillator circuit includes: a ring oscillator having delay elements delaying a pulse signal; a counter circuit counting the circulation number of the pulse signal; a rough period generation unit acquiring a period setting value as a magnification ratio for a reference clock, and counting the reference clock using an integer part of the ratio to generate a rough period timing; a fraction conversion unit converting a decimal point part of the ratio into the number of the elements passed by the pulse signal to generate a fraction; and an output processing unit selecting a timing when outputs of the ring oscillator and the counter circuit become values corresponding to the fraction as an output timing when a time corresponding to the fraction has passed after the rough period timing, and generating an output signal oscillating at a period represented by the period setting value according to the output timing.

Abstract: A demodulation device for demodulating a base signal from a composite signal, which is composed of a carrier wave and a sensor modulation signal of the base signal. The demodulation device determines a difference between the composite signal of a former-half period and the composite signal of a latter-half period to be a pre-correction base signal. The former-half period is a one-half period of a sampling period starting at one of a local maximum and a local minimum of the carrier wave. The latter-half period follows the former-half period. The demodulation device determines a reference level from the composite signal and determines a signal level of a post-correction base signal based on a ratio between a signal level of the pre-correction base signal and the reference level.

Abstract: A first encoding part encodes a reference timing determined by a reference clock by using a delay line. A second encoding part encodes a measurement start timing and a measurement end timing of a measurement period determined by a measurement signal to be measured by also using the delay line. A count part counts the reference clocks included in the measurement period. A fraction calculation part calculates a start fraction number indicating a time difference from the measurement start timing and an immediately-following reference timing and an end fraction number indicating a time difference from the measurement end timing to an immediately-following reference timing, based on the encoding result. The fraction calculation part then calculates a fraction data indicating a difference between the measurement period and a product of the period of the reference timing and the count value of the count part.