Abstract: A solid-state imaging device is capable of suppressing as much as possible an increase in power consumption of a low-frequency noise removing process. A pixel unit includes pixels outputting pixel signals corresponding to an amount of incident light and correction pixels outputting correction pixel signals corresponding to a correction reference voltage. An AD conversion circuit includes a delay circuit, to which a plurality of delay elements are connected, and outputs a digital signal corresponding to the number of delay elements through which a pulse signal passes when the pulse signal passes through the number of delay elements corresponding to a level of the pixel signal or the correction pixel signal.

Abstract: A gyro sensor includes a vibrator and a drive circuit. A PWM drive signal is applied to a pair of electrodes of the vibrator. The drive circuit outputs a high level signal and a low level signal to the electrodes as the PWM drive signal. The high level signal and the low level signal have potentials higher and lower than that of the reference signal, respectively. The drive circuit outputs the high level signal to one of the pair of electrodes and the low level signal to the other of the pair of electrodes.

Abstract: In a gyro sensor, a TDC detects a magnitude of vibration of a vibrator. A drive circuit (excluding the TDC) determines a duty ratio of a PWM drive signal in accordance with the magnitude of vibration so that the magnitude of vibration becomes a predetermined magnitude and outputs the PWM drive signal having the determined duty ratio. The drive circuit (excluding the TDC) includes a control circuit and a DCO. The control circuit measures time corresponding to the control value by using a gate delay time, generates the PWM drive signal having a pulse width corresponding to the control value and outputs the PWM drive signal.

Abstract: A digitally-controlled oscillator circuit receives a digital value and generates a driving signal for driving an oscillator at a frequency according to the received digital value. A time-to-digital converter circuit receives a detection signal of oscillation of the oscillator, receives the driving signal, and detects a phase difference between the detection signal and the driving signal. A control circuit receives the detected phase difference and controls the frequency of the driving signal generated by the digitally-controlled oscillator circuit, such that the detected phase difference coincides with a predetermined resonant phase difference to resonate the oscillator.

Abstract: An A/D conversion device includes an A/D conversion circuit that converts an inputted analog signal to digital data and outputs it, a digital signal correction unit that performs a correction process to the digital data and outputs a digital signal, and a phase compensation unit that performs phase compensation in accordance with a phase delay amount of the digital signal with respect to the analog signal generated in the A/D conversion circuit and the digital signal correction unit wherein the A/D conversion circuit comprises a pulse transit circuit, a transmit position detection structure, and a digital data creation structure, the delay characteristic of the digital data being identified from the inputted analog signal.

Abstract: The A/D conversion circuit may include A/D conversion units each of which converts input analog signals into digital signals, a switch unit that receives a first and second analog signals among the analog signals, the switch unit alternately switching output destinations of the first and second analog signals input in the same period to the A/D conversion units in each sampling cycle of the A/D conversion units; and an arithmetic unit that performs a differential operation between a result of addition of the digital signals output from the A/D conversion units to which the first analog signal is input and a result of addition of the digital signals output from the A/D conversion units which the second analog signal is input, the arithmetic unit outputting a third digital signal corresponding to a result of the differential operation.

Abstract: The physical quantity measuring apparatus includes a first function of generating voltage used for position-controlling a movable body, a second function of detecting a position of the movable body during a position detecting period, a third function of calculating a control amount necessary to keep the movable body at a predetermined position on the basis of a detection result by the second function, and causing the first function to generate a control voltage corresponding to the calculated control amount to keep the movable body at the predetermined position during a position controlling period, and a fourth function of setting the position detecting period and the position controlling period in a time-sharing manner so that the position detecting period and the position controlling period do not overlap with each other.

Abstract: A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.

Abstract: A transmitting method has steps of modulating carrier waves having frequencies set at ½N?n (n?N; n is a positive integer) of a reference frequency with transmission signals to produce modulated signals, multiplexing the modulated signals by frequency division multiplexing to produce an input signal, and transmitting the input signal to a synchronous detector in which the transmission signals are extracted from the input signal by calculating a moving average of the input signal every sampling period of time corresponding to the reference frequency and performing an addition and subtraction calculation corresponding to the cycle of each carrier wave for the moving averages. The frequency of each carrier wave, modulated with one transmission signal having a first signal level, is equal to or lower than the frequency of any carrier wave modulated with another transmission signal having a second signal level higher than the first signal level.

Abstract: The A/D conversion circuit may include A/D conversion units each of which converts input analog signals into digital signals, a switch unit that receives a first and second analog signals among the analog signals, the switch unit alternately switching output destinations of the first and second analog signals input in the same period to the A/D conversion units in each sampling cycle of the A/D conversion units; and an arithmetic unit that performs a differential operation between a result of addition of the digital signals output from the A/D conversion units to which the first analog signal is input and a result of addition of the digital signals output from the A/D conversion units which the second analog signal is input, the arithmetic unit outputting a third digital signal corresponding to a result of the differential operation.

Abstract: The pulse delay circuit includes a plurality of delay units connected in series or in a ring, each of the delay units being constituted of at least one inverter gate circuit grounded to a ground line, and configured to delay a pulse signal passing therethrough by a delay time thereof depending on an input signal applied thereto, and a capacitor connected between a signal line through which the voltage signal is applied to each of the delay units and the ground line. The capacitor serves as a current source to supply a current which each of the delay units consumes to invert a state thereof.

Abstract: In a feedback control device (100), a phase compensation unit (13) performs phase compensation in accordance with a phase delay generation in a time A/D conversion circuit (11), which converts an inputted analog signal to digital data, and in a digital signal correction unit (12), which corrects the digital data arbitrarily.

Abstract: A radio wave timepiece A and a quadrature detection device for executing a quadrature detecting method are disclosed including a receiving antenna 14 for receiving a carrier wave of a long wave standard radio wave on which time information is multiplexed, a quadrature detection circuit 18 for performing quadrature detection of the carrier wave in response to a reference clock CK1, commonly used for timekeeping by a time counter 8, to obtain an in-phase component I and a quadrature component Q of the carrier wave for obtaining an amplitude AN,m of the carrier wave, and a time correction means 22, 24, 26 for obtaining time information depending on the amplitude of the carrier wave from the quadrature detection circuit 18. The time counter 8 is responsive to time information delivered from the time correction means to correct current time.

Abstract: The even-number-stage pulse delay includes a ring delay line constituted of an even number of inverter circuits connected in a ring around which main edge and a reset edge circulate together. The even-number-stage pulse delay is provided with an operation monitoring section configured to detect whether or not the main and reset edges are circulating around the ring delay line.

Abstract: A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.

Abstract: An A/D converter has a series of M delay units through which a pulse signal is transmitted while being delayed in each delay unit by a delay time depending on a level of an analog signal. A unit of the converter latches the pulse signal outputted from each delay unit at N sampling times to hold M×N latched data. Another unit of the converter receives the M×N pieces of latched data as a piece of combined data composed of the latched data arranged in an order corresponding to an arranging order of M×N sampling points in the pulse signal, converts the combined data into numeral data, corresponding to a position of the pulse signal in the delay units, at one time, and produces converted digital data corresponding to the level of the analog signal from the numeral data.

Abstract: The even-number-stage pulse delay includes a ring delay line constituted of an even number of inverter circuits connected in a ring around which main edge and a reset edge circulate together. The even-number-stage pulse delay is provided with an operation monitoring section configured to detect whether or not the main and reset edges are circulating around the ring delay line.

Abstract: An inverter circuit configuring a delay unit is a so-called CMOS transistor including a PMOS transistor and an NMOS transistor, of which respective gates are interconnected and respective drains are interconnected. The source and a back gate of the NMOS transistor are connected to the ground. The source of the PMOS transistor is connected to a positive drive terminal and controlled by an analog input signal. The back gate of the PMOS transistor is connected to a control terminal and controlled by a control signal.

Abstract: The pulse delay circuit includes a plurality of delay units connected in series or in a ring, each of the delay units being constituted of at least one inverter gate circuit grounded to a ground line, and configured to delay a pulse signal passing therethrough by a delay time thereof depending on an input signal applied thereto, and a capacitor connected between a signal line through which the voltage signal is applied to each of the delay units and the ground line. The capacitor serves as a current source to supply a current which each of the delay units consumes to invert a state thereof.

Abstract: A pulse signal circulates around a ring of delay elements with respective traversal signals being thereby successively outputted from the delay elements. The period of a reference signal is multiplied or divided by a real number to obtain control data specifying a required period of a clock signal as a value having an integer part and a fractional part. The control data are used to select the timings of specific traversal signal, and the clock signal is generated based these selected timings, with the timing selection being repetitively adjusted in accordance with the fractional part of the control data.