Abstract: According to one embodiment, a display device includes a display panel having a counter substrate, an array substrate and a liquid crystal layer held therebetween, a counter electrode provided on the counter substrate, a pixel electrode arranged on the array substrate in a matrix, a sensor circuit arranged between rows of the plurality of pixel electrodes and configured to read out intensity of capacitive coupling between the sensor circuit and a dielectric, and a counter electrode drive circuit configured to pulsatively drive a common voltage added to the counter electrode during a period of driving the sensor circuit, wherein the sensor circuit comprises a detection electrode configured to form capacitance between the sensor circuit and the dielectric and to form capacitance between the sensor circuit and the counter electrode, and wherein the counter electrode comprises an aperture including at least a portion opposed to the detection electrode.

Abstract: According to one embodiment, a display device includes a display pixel allocated at a matrix state in a display area, an image-reading device which detects strength of capacitive coupling by a dielectric material coming close to or making contact with the display area, and a control portion which controls each transistor of the image-reading device. The image-reading device includes a detection electrode which forms capacitance between the detection electrode and the dielectric material, a pre-charge gate line, a coupling pulse line, a readout gate line, a pre-charge line and a readout line. These lines supply a signal which drives the image-reading device. The image-reading device further includes a pre-charge transistor, an amplification transistor, a readout transistor, a compensation transistor, and a power-source switching transistor.

Abstract: Provided is a waveform processing circuit including: an amplitude expansion circuit configured to expand amplitude of an analog video signal; a voltage shifting circuit configured to shift a voltage of the analog video signal; and an impedance conversion circuit having an output impedance lower than that of the voltage shifting circuit.

Abstract: According to one embodiment, a display apparatus includes signal lines, and pixels. Each of the pixels includes a pixel electrode and a pixel control switch, and being classified into any of pixel groups. Each of the pixel groups includes a memory, and a sensor circuit which is configured to provide data for a detection signal to the memory when detecting the input information. The pixel control switch is configured to switch the voltage level of the pixel electrode in accordance with data for the display signal input via the signal line and the data for the detection signal input from the memory.

Abstract: According to one embodiment, a print head includes first and second substrates, an OLED array and a drive circuit. The first substrate extending in a first direction and has a main surface including first to third regions. The first region extends in the first direction. The second and third regions are arranged in a second direction crossing the first direction with the first region interposed between the second and third regions. The OLED array includes first electrodes arranged above the first region, an organic emitting layer positioned above the first electrodes, and a second electrode positioned above the organic emitting layer. The drive circuit is configured to supply drive currents to the first electrodes and includes a first circuit positioned above the third region and a second circuit positioned above the third region.

Abstract: Provided is a waveform processing circuit including: an amplitude expansion circuit configured to expand amplitude of an analog video signal; a voltage shifting circuit configured to shift a voltage of the analog video signal; and an impedance conversion circuit having an output impedance lower than that of the voltage shifting circuit.

Abstract: A liquid crystal display apparatus includes a plurality of source lines and gate lines, pixel switching elements, and a plurality of drive circuits, each provided for a group of a predetermined number of source lines, and converting i-bit data video signal into an analog gradation signal and supplying the analog gradation signal to each of the source lines, the liquid crystal display apparatus performing gradation display with an ith power of 2, based on i-bit data, wherein the drive circuits each include a first switching circuit which selects the video signal, a digital to analog conversion circuit DAC which converts the video signal into the gradation signal, a second switching circuit which supplies the gradation signal to each source line, and a control circuit which controls an order of supplying the gradation signal to each source line to be different every n horizontal period and every m vertical period.

Abstract: A liquid crystal display according to one embodiment of the present invention, comprising: signal lines and scanning lines arranged in first and second directions on an insulation substrate; display elements formed in vicinity of cross points of the signal lines and scanning lines; liquid crystal capacitors and auxiliary capacitors which accumulate electric charge in accordance with voltages of the signal lines via said display elements; a signal line drive circuit which drives the signal lines; a scanning line drive circuit which drives the scanning lines; auxiliary capacitor power supply lines arranged in the first direction, to which one ends of said auxiliary capacitors arranged in the second direction are commonly connected; and auxiliary capacitor power supply line voltage control circuits which control voltages of said auxiliary capacitor power supply lines in sync with a cycle which drives said liquid crystal capacitors and said auxiliary capacitors by polarity reverse, wherein said auxiliary capacito

Abstract: In a flat panel display device configured to allow moving image data supplied through a signal line 11 to be written to a pixel electrode 13 during typical display operation and further to allow still image data latched in a digital memory 18 to be written to the pixel electrode 13 during still image display operation. When switching from a typical display to a still image display, at least two frames following the completion of the switching operation are assigned as write frames to allow still image data to be written to the digital memory 18. This allows the still image data to be written normally to the digital memory 18 even when the rise times of a memory control signal and a common signal are made longer than a vertical blanking period.

Abstract: In a flat panel display device in which driving circuits and the like are arranged on an array substrate, a technology to realize a compact size and a low cost of an external control circuit is disclosed. At least one pumping circuit included in the external control circuit is arranged on the array substrate, and an output side capacitor connected between an output portion of the pumping circuit and the ground GND and an input side capacitor of a clock input portion are arranged outside the array substrate.

Abstract: During a still picture display period, a normal write voltage is sometimes unable to be applied to a liquid crystal layer 16 because two memory switch elements 21 and 22 are simultaneously turned on, and the output and the inverted output from the digital memory 18 are applied simultaneously to a pixel electrode 13. According to the present invention, the pulse width for the on period of one of the memory switch elements 21 and 22 is narrower than the pulse width for the off period of the other memory switch element, so that the on periods of the two memory switch elements 21 and 22 do not overlap. In this manner, the memory switch elements 21 and 22 are prevented from being turned on at the same time.

Abstract: A liquid crystal display according to one embodiment of the present invention, comprising: signal lines and scanning lines arranged in first and second directions on an insulation substrate; display elements formed in vicinity of cross points of the signal lines and scanning lines; liquid crystal capacitors and auxiliary capacitors which accumulate electric charge in accordance with voltages of the signal lines via said display elements; a signal line drive circuit which drives the signal lines; a scanning line drive circuit which drives the scanning lines; auxiliary capacitor power supply lines arranged in the first direction, to which one ends of said auxiliary capacitors arranged in the second direction are commonly connected; and auxiliary capacitor power supply line voltage control circuits which control voltages of said auxiliary capacitor power supply lines in sync with a cycle which drives said liquid crystal capacitors and said auxiliary capacitors by polarity reverse, wherein said auxiliary capacito

Abstract: Disclosed is a circuit constitution of a display apparatus comprising a digital memory (DM) cell for each pixel. The DM cell is composed of one inverter circuit, and a DM switching circuit for controlling an electrical conduction between a pixel electrode and the DM cell is provided. During a normal displaying period, the DM cell and the pixel electrode are not electrically conducted by the DM switching circuit, and a full-color image displaying is performed by dynamic image data supplied to a signal line. During a still image displaying, the DM cell and the pixel electrode are electrically conducted by the DM switching circuit, and a multi-color image displaying is performed by still image data retained in the DM cell.

Abstract: A display has display pixels provided with digital memories, respectively. In each display pixel, a pixel electrode and a data line are connected to each other through a first switch, and the pixel electrode and the digital memory are connected to each other through a second switch. In a first display period, the second switches are turned off and the first switches are turned on, to display video data supplied from the data lines. In a second display period, the second switches are turned on and the first switches are turned off, to stop scan and data drivers and display video data stored in the digital memories.

Abstract: In a flat panel display device in which driving circuits and the like are arranged on an array substrate, a technology to realize a compact size and a low cost of an external control circuit is disclosed. At least one pumping circuit included in the external control circuit is arranged on the array substrate, and an output side capacitor connected between an output portion of the pumping circuit and the ground GND and an input side capacitor of a clock input portion are arranged outside the array substrate.

Abstract: In a flat panel display device configured to allow moving image data supplied through a signal line 11 to be written to a pixel electrode 13 during typical display operation and further to allow still image data latched in a digital memory 18 to be written to the pixel electrode 13 during still image display operation. When switching from a typical display to a still image display, at least two frames following the completion of the switching operation are assigned as write frames to allow still image data to be written to the digital memory 18. This allows the still image data to be written normally to the digital memory 18 even when the rise times of a memory control signal and a common signal are made longer than a vertical blanking period.

Abstract: There is provided a driving circuit including active matrix type liquid crystal display capable of decreasing the electric power consumption of CMOS buffers contained in a scanning line driving circuit and picture signal line driving circuit. The liquid crystal display has an active matrix type liquid crystal display elements comprising switching elements connected to a plurality of scanning lines and a plurality of picture signal lines perpendicular to the scanning lines. The liquid crystal display includes a digital circuit wherein at least one of a scanning line driving circuit for applying a scanning pulse to the switching elements via the scanning lines and a picture signal line driving circuit for applying a picture signal to the picture signal lines comprises one stage of CMOS buffer or a plurality of CMOS buffers connected in multi stages, the CMOS transistor or each of the CMOS transistors including an N-type thin-film transistor and P-type thin-film transistor which are formed on the same substrate.

Abstract: During a still picture display period, a normal write voltage is sometimes unable to be applied to a liquid crystal layer 16 because two memory switch elements 21 and 22 are simultaneously turned on, and the output and the inverted output from the digital memory 18 are applied simultaneously to a pixel electrode 13. According to the present invention, the pulse width for the on period of one of the memory switch elements 21 and 22 is narrower than the pulse width for the off period of the other memory switch element, so that the on periods of the two memory switch elements 21 and 22 do not overlap. In this manner, the memory switch elements 21 and 22 are prevented from being turned on at the same time.

Abstract: In a flat panel display device in which driving circuits and the like are arranged on an array substrate, a technology to realize a compact size and a low cost of an external control circuit is disclosed. At least one pumping circuit included in the external control circuit is arranged on the array substrate, and an output side capacitor connected between an output portion of the pumping circuit and the ground GND and an input side capacitor of a clock input portion are arranged outside the array substrate.

Abstract: Disclosed is a circuit constitution of a display apparatus comprising a digital memory (DM) cell for each pixel. The DM cell is composed of one inverter circuit, and a DM switching circuit for controlling an electrical conduction between a pixel electrode and the DM cell is provided. During a normal displaying period, the DM cell and the pixel electrode are not electrically conducted by the DM switching circuit, and a full-color image displaying is performed by dynamic image data supplied to a signal line. During a still image displaying, the DM cell and the pixel electrode are electrically conducted by the DM switching circuit, and a multi-color image displaying is performed by still image data retained in the DM cell.