Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Abstract: A process for producing a polymer having sulfonic acid groups is provided which comprises treating a polymer having sulfonate salt groups with a ion-exchange resin to change the sulfonate salt groups into sulfonate acid groups with porous-type strongly acidic cation exchange resin. A process for producing a tertiary alcohol is also provided which comprises hydration of olefin by use of the aforementioned polymer as the catalyst. By the process, a tertiary alcohol is produced by hydration of olefin with high selectivity at low cost.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Abstract: A dynamic address translation processing apparatus in a data processing system having a main memory for storing an address conversion table, and a central processing unit for converting a virtual address to a real address by referring the address conversion table. The central processing unit includes a first register for holding the virtual address, a second register for holding a table entry of the address conversion table corresponding to the virtual address held in the first register and, having an update bit indicative that a page in memory has been written to a third register for holding the real address of the table entry held in the second register, a comparison circuit for comparing the virtual address held in the first register with the other virtual address to be converted to the real address, and an update unit for updating the update bit in the table entry held in the second register.

Abstract: An instructing method for specifying an instruction which is to be executed in an information processing apparatus, forms each of instruction words from at least an instruction code and an operand specifying part for specifying a single instruction, forms each of long instruction words having a fixed length from a type code and one or plurality of the instruction words, where the type code specifies a structure of the one or plurality of the instruction words included in the long instruction word, and specifies one or plurality of instructions by a the long instruction word.

Abstract: An assembly that includes a frame, a pair of containers fitted to the frame, a common closure, and an operating assembly for moving the common closure. Each of the pair of containers is constituted by a syringe, and a nozzle portion is formed at the front end of container body of the syringe. The operating assembly includes an operating lever pivotably mounted on the frame, and the common closure is pivotably mounted on the operating lever. The common closure has a pair of cap portions that are fitted to the nozzle portions. When the operating lever is turned in the closing direction up to a predetermined final position, the common closure is moved together with the operating lever, brought to a turning position which is opposed to the nozzle positions, and upon relative rotation of the operating lever with respect to the closure, the closure is further moved toward the nozzle portions.

Abstract: In a pixel density converting apparatus according to the present invention, a pixel density conversion element for converting a pixel density by a factor of an arbitrary value, such as an element of the projection method or the linear interpolation method, a pixel density conversion element for increasing or decreasing a pixel density by a factor of an integer, such as an element of the majority or logical OR method, and a binarization element for conducting binarization while correcting quantizing errors, such as an element of the error diffusion method or the average error minimizing method, are combined with each other with the advantages and disadvantages of the respective elements taken into consideration, so as to achieve excellent conversion whether or not the image on which pixel density conversion is conducted or an image area is a pseudo half-tone processed image.

Abstract: In a pixel density converting apparatus according to the present invention, a pixel density conversion element for converting a pixel density by a factor of an arbitrary value, such as an element of the projection method or the linear interpolation method, a pixel density conversion element for increasing or decreasing a pixel density by a factor of an integer, such as an element of the majority or logical OR method, and a binarization element for conducting binarization while correcting quantizing errors, such as an element of the error diffusion method or the average error minimizing method, are combined with each other with the advantages and disadvantages of the respective elements taken into consideration, so as to achieve excellent conversion whether or not the image on which pixel density conversion is conducted or an image area is a pseudo half-tone processed image.

Abstract: A biCMOS integrated circuit is created on a p-type semiconductor substrate on which first an n-type epitaxial layer then a p-type epitaxial layer is grown. NPN and PMOS transistors are formed in n-wells in the p-type epitaxial layer. n.sup.+ buried layers are located below the n-wells at the interface between the substrate and the n-type epitaxial layer. The n.sup.+ buried layers underlying the n-wells containing NPN transistors are surrounded by p.sup.+ buried layers that extend from the interface between the p-type and n-type epitaxial layers through the n-type epitaxial layers and into the substrate.

Abstract: A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges. The process can be used to form wafer alignment marks having arbitrary patterns and can be adopted to improve the reliability of automatic alignment without the need to make new masks.

Abstract: A wafer alignment mark consists of patterns, such as a chevron and two stripes, formed in the surface of a semiconductor wafer. Each pattern is defined by a pair of parallel grooves, separation between all pairs of grooves being the same. Each groove provides one sharp edge which can be reliably detected by an automatic alignment system.A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges.

Abstract: A biCMOS integrated circuit is created on a p-type semiconductor substrate on which first an n-type epitaxial layer then a p-type epitaxial layer is grown. NPN and PMOS transistors are formed in n-wells in the p-type epitaxial layer. n.sup.+ buried layers are located below the n-wells at the interface between the substrate and the n-type epitaxial layer. The n.sup.+ buried layers underlying the n-wells containing NPN transistors are surrounded by p.sup.+ buried layers that extend from the interface between the p-type and n-type epitaxial layers through the n-type epitaxial layer and into the substrate.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunkline, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Abstract: A field-effect transistor wherein a gate electrode conductive layer is connected in parallel to a plurality of conductive layers having a lower resistivity than the gate electrode conductive layer, so that the gate resistance is reduced to provide a high power output and a noise reduction.

Abstract: Storm water pumps drain storm water in a pump well. In order to control the storm water pumps, a radar rain gage and ground raingages are set. Measurement data from the radar rain gage and the ground rain gages are supplied to a data processing unit. The data processing unit calibrates rainfall distribution data representing a two-dimensional rainfall distribtuion state obtained by the radar rain gate by the measurement data from the ground rain gages, and forecasts a rainfall in a predetermined time from the present from several sets of the calibrated rainfall distribution data. The data processing unit performs runoff analysis corresponding to characteristics of a drainage basin on the basis of the forecast rainfall to calculate a rainfall flow, thereby forecasting a flow of storm water flowing in the pump well.

Abstract: A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.

Abstract: A field-effect transistor wherein a gate electrode conductive layer is connected in parallel to a plurality of conductive layers having a lower resistivity than the gate electrode conductive layer, so that the gate resistance is reduced to provide a high power output and a noise reduction.

Abstract: A printer having a first memory for storing character data representative of lines of characters to be printed on a recording medium, a second memory for storing line-space data representative of a line spacing between the lines of characters, and a control device for activating a print head according to the character data stored in the first memory, and controlling the print head and a paper feed device according to the line-space data stored in the second memory, to underscore at least one of the characters of the printed lines. The position of the underscore is controlled such that a distance between the underscore and the underscored characters is varied depending upon the line spacing represented by the line-space data.

Abstract: Described is a polysaccharide polyol derived from Volvariella volvacea, which is comprised of the following three types of recurring units. ##STR1## wherein D-Glu is D-glucopyranosyl residue, each number represents the linkage position, X is HOCH.sub.2 CH(CH.sub.2 OH)--O--CH(CH.sub.2 OH)--O--[Formula A] or D-glucopyranosyl and Y is --CH.sub.2 --CH(CH.sub.2 OH)--O--CH(CH.sub.2 OH)--O-- or D-glucopyranosyl, at least a part of X in the recurring units II and III is that of formula A, and, the average number of III is about 4-12 and the average number of the sum II and III is about 16-23, per 100 of the sum of I, II and III. The polysaccharide is prepared by extracting Volvariella volvacea with an aqueous alkali solution and oxidizing and then reducing the soluble fraction to cut parts of C--C bonds of side chains. The polysaccharide is useful and an anti-tumor agent.

Abstract: A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.