Patents by Inventor Takao Matsumoto

Takao Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200025443
    Abstract: The present invention aims to provide a method and an apparatus for producing a lyophilized body, each of which can achieve energy saving, low cost, and a reduction in processing time and can provide a lyophilized body less damaged by a freezing process and a drying process. The present invention relates to a method for lyophilizing a substance using an electromagnetic wave, and the lyophilization method includes freezing the substance under irradiation of at least an electromagnetic wave and reduced-pressure drying the frozen substance under irradiation of at least an electromagnetic wave.
    Type: Application
    Filed: April 2, 2018
    Publication date: January 23, 2020
    Applicant: NITTO DENKO CORPORATION
    Inventors: Chie MATSUMOTO, Takao YOSHIKAWA, Takuya SHISHIDO, Yuji TOYOTA, Sachiko SAKAMOTO, Yoshimitsu SHIMOMURA, Mitsuhiko HORI
  • Publication number: 20200006394
    Abstract: A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is lower in crystallinity than the first region and the second region.
    Type: Application
    Filed: March 22, 2019
    Publication date: January 2, 2020
    Inventors: YUTA SUGAWARA, MASAKAZU TANAKA, NOBUTAKE NODERA, TAKAO MATSUMOTO
  • Publication number: 20200006396
    Abstract: A thin film transistor includes: a gate electrode supported on a substrate; a gate insulating layer that covers the gate electrode; an oxide semiconductor layer provided on the gate insulating layer and having a crystalline region, the crystalline region including a first region, a second region, and a channel region located between the first region and the second region, wherein the channel region, the first region and the second region overlap with the gate electrode with the gate insulating layer interposed therebetween; a protection insulating layer arranged on the oxide semiconductor layer so that the channel region is covered and the first region and the second region are exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region, wherein a crystallinity of the channel region is different from a crystallinity of the first region and the second region.
    Type: Application
    Filed: April 2, 2019
    Publication date: January 2, 2020
    Inventors: YUTA SUGAWARA, SATOSHI MICHINAKA, NOBUTAKE NODERA, TAKAO MATSUMOTO
  • Publication number: 20200006395
    Abstract: A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is higher in crystallinity than the first region and the second region.
    Type: Application
    Filed: April 1, 2019
    Publication date: January 2, 2020
    Inventors: YUTA SUGAWARA, TAKESHI UNO, NOBUTAKE NODERA, TAKAO MATSUMOTO
  • Publication number: 20190355486
    Abstract: Provided is a control rod motion monitoring method and a control rod motion monitoring system, in which a control rod insertion in an entire core is monitored at all time during operation of a reactor and, when an abnormality occurs, a signal is issued to a countermeasure device that automatically starts operation and an alarm is issued to prompt operation of an operator. An LPRM detector in an LPRM assembly of the entire core is divided into four channels for each height; indicated values are averaged at all time; the average indicated value is compared with a set point; and a signal is issued to a countermeasure device when an abnormality occurs.
    Type: Application
    Filed: January 12, 2017
    Publication date: November 21, 2019
    Inventors: Satoshi TAKEO, Akira KONOMA, Akiyuki TSUCHIYA, Koji MATSUMOTO, Takao KONDO, Yuji HONMA
  • Patent number: 10453876
    Abstract: In the present invention, a gate electrode is formed on a substrate surface, and an insulation film is formed on the substrate surface whereon the gate electrode has been formed. A first amorphous silicon layer is formed on the substrate surface whereon the insulation film has been formed. An energy beam is irradiated onto a plurality of required sites spaced from each other in the first amorphous silicon layer to transform each of the required sites into a polysilicon layer. Each of the required sites is situated on the upper side of the gate electrode and serves as a channel region between a source and a drain. This allows other sites, which are in the first amorphous silicon layer and related to the plurality of required sites, to also be irradiated by the energy beam and ablated so as to form at the other sites a cleared portion having a required shape.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 22, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto
  • Patent number: 10413952
    Abstract: This gate device is provided with a guide unit having a guide section that is disposed at the downstream side of pinch rollers at a path line along which a metal sheet is conveyed, opens/closes a coil-up line that is curved from the path line, and guides the upwards-facing surface side of the metal sheet led in to the coil-up line. A configuration is adopted such that the guide unit has a main body frame and a liner that is attached to the main body frame, forms at least a portion of the second guide surface that guides the metal sheet, has a lower coefficient of friction than the main body frame, and has a lower hardness than that of the metal sheet.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 17, 2019
    Assignees: PRIMETALS TECHNOLOGIES JAPAN, LTD., JFE STEEL CORPORATION
    Inventors: Hiroshi Matsumoto, Yusuke Ogaki, Takayuki Endo, Takao Uchiyama, Tsutomu Sugiyama, Takeshi Chiba
  • Patent number: 10406578
    Abstract: A coiler device (1), provided with a chute roller (50), has: pinch rollers (10a, 10b) that lead a metal sheet carried in along a path line (L1) to a coil-up line (L2) that is curved from the path line (L1); a mandrel (20) that coils the metal sheet and is disposed ahead of the coil-up line (L2); and a chute roller (50) that exposes at least the leading end of the metal sheet to the coil-up line (L2) when being wound to the mandrel (20), and suppresses curving of the metal sheet toward a surface of the metal sheet facing the chute roller (50).
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 10, 2019
    Assignees: PRIMETALS TECHNOLOGIES JAPAN, LTD., JFE STEEL CORPORATION
    Inventors: Hiroshi Matsumoto, Masahiro Kuchi, Yuji Kanko, Takayuki Endo, Takao Uchiyama, Tsutomu Sugiyama, Takeshi Chiba
  • Publication number: 20190267235
    Abstract: A laser irradiation apparatus includes a light source that generates a laser beam, a projection lens that radiates the laser beam onto a predetermined region of an amorphous silicon thin film deposited on each of a plurality of thin film transistors on a glass substrate, and a projection mask pattern provided on the projection lens and has a plurality of openings so that the laser beam is radiated onto each of the plurality of thin film transistors, wherein the projection lens radiates the laser beam onto the plurality of thin film transistors on the glass substrate, which moves in a predetermined direction, through the projection mask pattern, and the projection mask pattern is provided such that the openings are not continuous in one column orthogonal to the moving direction.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Michinobu Mizumura, Nobutake Nodera, Yoshiaki Matsushima, Masakazu Tanaka, Takao Matsumoto
  • Publication number: 20190214157
    Abstract: A control rod operation generates a rod insertion block signal during operation of a reactor. Four neutron detector assemblies including a plurality of LPRMs arranged in an axial direction of a core are arranged adjacent to a plurality of insertion selection control rods, respectively, which are simultaneously inserted into the core. Neutron flux ratio calculation units are arranged in each of the neutron detector assemblies, and ratios (neutron flux ratios BA/AA, CA/AA, and DA/AA) of an average LPRM signal of the respective LPRMs at positions B, C, and D to an average LPRM signal of the respective LPRMs at a position A which is closest to the control rod insertion end of the core are calculated. When the largest neutron flux ratio out of the neutron flux ratios exceeds a set neutron flux ratio, a rod insertion block signal which is generated by a local range rod insertion monitor is output.
    Type: Application
    Filed: November 25, 2016
    Publication date: July 11, 2019
    Inventors: Koji MATSUMOTO, Kazuya ISHII, Takao KONDOU, Akira KONOMA, Akiyuki TSUCHIYA
  • Patent number: 10310347
    Abstract: There are provided a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes a pixel having a first thin film transistor and a drive circuit having a second thin film transistor and driving the pixel, wherein a first channel region of the first thin film transistor and a second channel region of the second thin film transistor are configured to have different electrical characteristics (for example, electron mobility, thereby enabling the first thin film transistor and the second thin film transistor to function suitably for the each role thereof).
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: June 4, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryouhei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10293392
    Abstract: This coiler device provided with a chute guide has: pinch rollers that lead a metal sheet carried in along a path line to a coil-up line that is curved from the path line; a mandrel that is disposed ahead of the coil-up line and coils up the metal sheet; and a chute guide that guides the upward-facing surface side of the metal sheet at the coil-up line and introduces the metal sheet to the coil-up opening of the mandrel. A configuration is adopted such that the chute guide has: a main body frame; and a liner that is attached to the main body frame, forms at least a portion of the guide surface that guides the metal sheet, has a lower coefficient of friction than the main body frame, and has a lower hardness than the metal sheet.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: May 21, 2019
    Assignees: PRIMETALS TECHNOLOGIES JAPAN, LTD., JFE STEEL CORPORATION
    Inventors: Hiroshi Matsumoto, Koichi Arai, Takayuki Endo, Takao Uchiyama, Tsutomu Sugiyama, Takeshi Chiba
  • Publication number: 20190137007
    Abstract: There is provided a hose clamp. A clamp has a clamp body. On one end portion of the clamp body, a slit is provided and a first grip piece is formed. On the other end portion of the clamp body, a second grip piece is formed. A holder is provided with a holding groove and a grip portion. The holding groove has an insertion opening opened in a direction intersecting with an axial direction of the clamp body, and a side opening opened on at least one end side in the axial direction of the clamp body. A protrusion is provided on at least one of opposing inner surfaces of the holding groove. When the pair of grip pieces are inserted in the holding groove, the protrusion can be arranged inside a part of the slit located in the first grip piece.
    Type: Application
    Filed: November 2, 2018
    Publication date: May 9, 2019
    Inventors: Takao Nagai, Tomoyuki Matsumoto
  • Publication number: 20190140102
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Application
    Filed: April 25, 2016
    Publication date: May 9, 2019
    Applicant: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: YOSHIAKI MATSUSHIMA, SHIGERU ISHIDA, RYOHEI TAKAKURA, SATORU UTSUGI, NOBUTAKE NODERA, TAKAO MATSUMOTO, SATOSHI MICHINAKA
  • Patent number: 10263121
    Abstract: Provided are a thin film transistor having properties properly adjusted by adjusting crystallinity of a polycrystalline silicon, and a method of manufacturing the same. The silicon layer functioning as a channel layer of a TFT comprises an amorphous part, a first polycrystalline part and a second polycrystalline part. The first and second polycrystalline parts are formed by irradiating the silicon layer with laser beams (energy beams) through the mask comprising the shielding part for shielding the energy beams, the first transmission part for transmitting the energy beams and the second transmission part for transmitting the energy beams at a transmittance lower than that of the first transmission part. By the presence of the second polycrystalline part, properties of the TFT such as an electron mobility are properly adjusted. Further, properties of the TFT can be adjusted easily by adjusting the configuration of the mask.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 16, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Yoshiaki Matsushima, Shigeru Ishida, Ryouhei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10256350
    Abstract: A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer including an amorphous silicon, irradiating a region of the first silicon layer from a part or the whole of a predetermined region of the first silicon layer to an outside of the predetermined region with an energy beam so as to convert a portion of the first silicon layer into a polycrystalline silicon, a first etching step for etching the first silicon layer while leaving the predetermined region, forming a second silicon layer including an amorphous silicon so as to cover the predetermined region, a second etching step for etching the second silicon layer covering the predetermined region while leaving a part of the second silicon layer, the part larger than the predetermined region, and forming a source electrode and a drain electrode.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 9, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Satoru Utsugi, Shigeru Ishida, Ryouhei Takakura, Yoshiaki Matsushima, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10243003
    Abstract: The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrod
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10038098
    Abstract: The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: July 31, 2018
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20180212065
    Abstract: Provided are a thin film transistor having properties properly adjusted by adjusting crystallinity of a polycrystalline silicon, and a method of manufacturing the same. The silicon layer functioning as a channel layer of a TFT comprises an amorphous part, a first polycrystalline part and a second polycrystalline part. The first and second polycrystalline parts are formed by irradiating the silicon layer with laser beams (energy beams) through the mask comprising the shielding part for shielding the energy beams, the first transmission part for transmitting the energy beams and the second transmission part for transmitting the energy beams at a transmittance lower than that of the first transmission part. By the presence of the second polycrystalline part, properties of the TFT such as an electron mobility are properly adjusted. Further, properties of the TFT can be adjusted easily by adjusting the configuration of the mask.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 26, 2018
    Inventors: Yoshiaki Matsushima, Shigeru Ishida, Ryouhei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto
  • Publication number: 20180204957
    Abstract: A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer including an amorphous silicon, irradiating a region of the first silicon layer from a part or the whole of a predetermined region of the first silicon layer to an outside of the predetermined region with an energy beam so as to convert a portion of the first silicon layer into a polycrystalline silicon, a first etching step for etching the first silicon layer while leaving the predetermined region, forming a second silicon layer including an amorphous silicon so as to cover the predetermined region, a second etching step for etching the second silicon layer covering the predetermined region while leaving a part of the second silicon layer, the part larger than the predetermined region, and forming a source electrode and a drain electrode.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 19, 2018
    Inventors: Satoru Utsugi, Shigeru Ishida, Ryouhei Takakura, Yoshiaki Matsushima, Nobutake Nodera, Takao Matsumoto