Patents by Inventor Takao Matsumoto

Takao Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194497
    Abstract: In a substrate processing apparatus (1), above a plurality of processing parts (31) arrayed in an up-and-down direction, arranged are a plurality of collecting pipes (61a to 61c). The plurality of collecting pipes (61a to 61c) correspond to a plurality of fluid classifications, respectively. Further, provided are a plurality of exhaust pipes (4) extending upward from the plurality of processing parts (31), into which exhaust gases from the processing parts (31) flow, respectively. At an upper end portion of each of the exhaust pipes (4), provided is a flow path switching part (5) which connects the upper end portion to the plurality of collecting pipes (61a to 61c) and switches a flow path of the exhaust gas flowing in the exhaust pipe (4) among the plurality of collecting pipes (61a to 61c). In the substrate processing apparatus (1), it is possible to reduce a pressure loss in the exhaust pipe (4) and reduce a footprint.
    Type: Application
    Filed: January 23, 2024
    Publication date: June 13, 2024
    Inventors: Hajime NISHIDE, Kwichang KANG, Takao MATSUMOTO
  • Patent number: 11955559
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 9, 2024
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yoshiaki Matsushima, Shigeru Ishida, Ryohei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto, Satoshi Michinaka
  • Patent number: 11915945
    Abstract: In a substrate processing apparatus (1), above a plurality of processing parts (31) arrayed in an up-and-down direction, arranged are a plurality of collecting pipes (61a to 61c). The plurality of collecting pipes (61a to 61c) correspond to a plurality of fluid classifications, respectively. Further, provided are a plurality of exhaust pipes (4) extending upward from the plurality of processing parts (31), into which exhaust gases from the processing parts (31) flow, respectively. At an upper end portion of each of the exhaust pipes (4), provided is a flow path switching part (5) which connects the upper end portion to the plurality of collecting pipes (61a to 61c) and switches a flow path of the exhaust gas flowing in the exhaust pipe (4) among the plurality of collecting pipes (61a to 61c). In the substrate processing apparatus (1), it is possible to reduce a pressure loss in the exhaust pipe (4) and reduce a footprint.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 27, 2024
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Hajime Nishide, Kwichang Kang, Takao Matsumoto
  • Publication number: 20210391475
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Inventors: YOSHIAKI MATSUSHIMA, SHIGERU ISHIDA, RYOHEI TAKAKURA, SATORU UTSUGI, NOBUTAKE NODERA, TAKAO MATSUMOTO, SATOSHI MICHINAKA
  • Patent number: 11133333
    Abstract: A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is lower in crystallinity than the first region and the second region.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 28, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yuta Sugawara, Masakazu Tanaka, Nobutake Nodera, Takao Matsumoto
  • Publication number: 20210210364
    Abstract: In a substrate processing apparatus (1), above a plurality of processing parts (31) arrayed in an up-and-down direction, arranged are a plurality of collecting pipes (61a to 61c). The plurality of collecting pipes (61a to 61c) correspond to a plurality of fluid classifications, respectively. Further, provided are a plurality of exhaust pipes (4) extending upward from the plurality of processing parts (31), into which exhaust gases from the processing parts (31) flow, respectively. At an upper end portion of each of the exhaust pipes (4), provided is a flow path switching part (5) which connects the upper end portion to the plurality of collecting pipes (61a to 61c) and switches a flow path of the exhaust gas flowing in the exhaust pipe (4) among the plurality of collecting pipes (61a to 61c). In the substrate processing apparatus (1), it is possible to reduce a pressure loss in the exhaust pipe (4) and reduce a footprint.
    Type: Application
    Filed: August 22, 2019
    Publication date: July 8, 2021
    Inventors: Hajime NISHIDE, Kwichang KANG, Takao MATSUMOTO
  • Patent number: 11004682
    Abstract: Provided are a laser annealing apparatus, a laser annealing method, and a mask with which scan nonuniformity can be decreased. According to the present invention, all or some openings of a plurality of openings are configured so that a partial subregion of a prescribed region is irradiated with laser light. The plurality of openings are configured so that, between prescribed regions irradiated with laser light via a group of openings in one row arranged in a row direction and prescribed regions irradiated with laser light via a group of openings in another row arranged in the row direction, the number of times of laser light radiations in subregions having the same occupying region is the same, and at least two openings of a group of openings arranged in a column direction have different positions or shapes.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: May 11, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yoshiaki Matsushima, Takeshi Uno, Yuta Sugawara, Kota Imanishi, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10937651
    Abstract: A laser annealing method includes: step A of providing a substrate having an amorphous semiconductor film formed on a surface thereof; and step B of selectively irradiating a portion of the amorphous semiconductor film with laser light. The step B includes a step of simultaneously forming, in the portion, two molten regions that have elongate shapes congruent to each other and are arranged in line symmetry with each other.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 2, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Masakazu Tanaka, Shinji Koiwa, Kouichi Karatani, Akihiro Shinozuka, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10896817
    Abstract: A laser irradiation apparatus includes a light source that generates a laser beam, a projection lens that radiates the laser beam onto a predetermined region of an amorphous silicon thin film deposited on each of a plurality of thin film transistors on a glass substrate, and a projection mask pattern provided on the projection lens and has a plurality of openings so that the laser beam is radiated onto each of the plurality of thin film transistors, wherein the projection lens radiates the laser beam onto the plurality of thin film transistors on the glass substrate, which moves in a predetermined direction, through the projection mask pattern, and the projection mask pattern is provided such that the openings are not continuous in one column orthogonal to the moving direction.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: January 19, 2021
    Assignees: V Technology Co. Ltd., Sakai Display Products Corporation
    Inventors: Michinobu Mizumura, Nobutake Nodera, Yoshiaki Matsushima, Masakazu Tanaka, Takao Matsumoto
  • Patent number: 10770483
    Abstract: A thin film transistor includes: a gate electrode supported on a substrate; a gate insulating layer that covers the gate electrode; an oxide semiconductor layer provided on the gate insulating layer and having a crystalline region, the crystalline region including a first region, a second region, and a channel region located between the first region and the second region, wherein the channel region, the first region and the second region overlap with the gate electrode with the gate insulating layer interposed therebetween; a protection insulating layer arranged on the oxide semiconductor layer so that the channel region is covered and the first region and the second region are exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region, wherein a crystallinity of the channel region is different from a crystallinity of the first region and the second region.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 8, 2020
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yuta Sugawara, Satoshi Michinaka, Nobutake Nodera, Takao Matsumoto
  • Publication number: 20200243242
    Abstract: A magnetic element is formed from a magnetic material, which is a material that is capable of generating a magnetic skyrmion, and a defect is introduced at a position corresponding to each side of an approximate triangle in plan view. A magnetic field having such a direction and an intensity as to generate at least one magnetic skyrmion in an area corresponding to inside of the approximate triangle is applied to the magnetic material with the defects introduced therein. This causes the magnetic skyrmion to be generated in the area corresponding to inside of the approximate triangle. This configuration enables the generated magnetic skyrmion to be stably kept at a higher temperature.
    Type: Application
    Filed: May 1, 2018
    Publication date: July 30, 2020
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Naoya SHIBATA, Takao MATSUMOTO
  • Publication number: 20200122996
    Abstract: A coffee machine 1 having a body part 3, a door 2 that is openably and closably supported by the body part 3 and a cup station at which a cup is placed, the coffee machine 1 supplying milk from a milk nozzle 25 a distal end of which is disposed above the cup, to the cup placed at the cup station, in which the coffee machine 1 includes a movable nozzle support unit 27 that supports the milk nozzle 25 and is disposed in the body part 3 so as to be movable between a first position at which the distal end of the milk nozzle 25 is above the cup while the door 2 is closed and a second position at which the distal end of the milk nozzle 25 is retracted from above the cup and a nozzle movement unit 50 that moves a pusher 52 so as to extend to and retract from the door 2. The pusher 52 is extended to push the movable nozzle support unit 27 and move the movable nozzle support unit 27 to a supply position.
    Type: Application
    Filed: April 23, 2018
    Publication date: April 23, 2020
    Inventors: Takao MATSUMOTO, Shinya ARAI
  • Patent number: 10620538
    Abstract: The present invention provides a positive type photosensitive siloxane composition in which a film formed by the same has high heat resistance, high strength and high crack resistance, an active matrix substrate in which by-product is not generated, an occurrence of defects is suppressed, and an interlayer insulating film is easily formed at a low cost while having good transmittance, a display apparatus including the active matrix substrate, and a method of manufacturing the active matrix substrate. An active matrix substrate includes a plurality of gate wirings provided so as to extend parallel to each other on an insulating substrate, and a plurality of source wirings provided so as to extend parallel to each other in a direction intersecting the respective gate wirings. An interlayer insulating film and a gate insulating film are interposed at portions including the intersecting portions of the gate wirings and the source wirings, on a lower side of the source wiring.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: April 14, 2020
    Assignees: Sakai Display Products Corporation, AZ ELECTRONIC MATERIALS (LUXEMBOURG) S.A.R.L.
    Inventors: Nobutake Nodera, Akihiro Shinozuka, Shinji Koiwa, Masahiro Kato, Takao Matsumoto, Takashi Fuke, Daishi Yokoyama, Katsuto Taniguchi
  • Publication number: 20200098557
    Abstract: Provided are a laser annealing apparatus, a laser annealing method, and a mask with which scan nonuniformity can be decreased. According to the present invention, all or some openings of a plurality of openings are configured so that a partial subregion of a prescribed region is irradiated with laser light. The plurality of openings are configured so that, between prescribed regions irradiated with laser light via a group of openings in one row arranged in a row direction and prescribed regions irradiated with laser light via a group of openings in another row arranged in the row direction, the number of times of laser light radiations in subregions having the same occupying region is the same, and at least two openings of a group of openings arranged in a column direction have different positions or shapes.
    Type: Application
    Filed: December 15, 2016
    Publication date: March 26, 2020
    Inventors: YOSHIAKI MATSUSHIMA, TAKESHI UNO, YUTA SUGAWARA, KOTA IMANISHI, NOBUTAKE NODERA, TAKAO MATSUMOTO
  • Patent number: 10559600
    Abstract: A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is higher in crystallinity than the first region and the second region.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: February 11, 2020
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yuta Sugawara, Takeshi Uno, Nobutake Nodera, Takao Matsumoto
  • Publication number: 20200043729
    Abstract: A laser annealing method includes: step A of providing a substrate having an amorphous semiconductor film formed on a surface thereof; and step BF of selectively irradiating a portion of the amorphous semiconductor film with laser light. Step B includes a step of simultaneously forming, in said portion, a first melted region that is elongated in a first direction and a second direction that is elongated in a second melted region different from the first direction.
    Type: Application
    Filed: July 3, 2019
    Publication date: February 6, 2020
    Inventors: Masakazu Tanaka, Shinji Koiwa, Kouichi Karatani, Akihiro Shinozuka, Nobutake Nodera, Takao Matsumoto
  • Publication number: 20200043731
    Abstract: A laser annealing method includes: step A of providing a substrate having an amorphous semiconductor film formed on a surface thereof; and step B of selectively irradiating a portion of the amorphous semiconductor film with laser light. The step B includes a step of simultaneously forming, in the portion, two molten regions that have elongate shapes congruent to each other and are arranged in line symmetry with each other.
    Type: Application
    Filed: July 3, 2019
    Publication date: February 6, 2020
    Inventors: MASAKAZU TANAKA, SHINJI KOIWA, KOUICHI KARATANI, AKIHIRO SHINOZUKA, NOBUTAKE NODERA, TAKAO MATSUMOTO
  • Publication number: 20200006395
    Abstract: A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is higher in crystallinity than the first region and the second region.
    Type: Application
    Filed: April 1, 2019
    Publication date: January 2, 2020
    Inventors: YUTA SUGAWARA, TAKESHI UNO, NOBUTAKE NODERA, TAKAO MATSUMOTO
  • Publication number: 20200006396
    Abstract: A thin film transistor includes: a gate electrode supported on a substrate; a gate insulating layer that covers the gate electrode; an oxide semiconductor layer provided on the gate insulating layer and having a crystalline region, the crystalline region including a first region, a second region, and a channel region located between the first region and the second region, wherein the channel region, the first region and the second region overlap with the gate electrode with the gate insulating layer interposed therebetween; a protection insulating layer arranged on the oxide semiconductor layer so that the channel region is covered and the first region and the second region are exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region, wherein a crystallinity of the channel region is different from a crystallinity of the first region and the second region.
    Type: Application
    Filed: April 2, 2019
    Publication date: January 2, 2020
    Inventors: YUTA SUGAWARA, SATOSHI MICHINAKA, NOBUTAKE NODERA, TAKAO MATSUMOTO
  • Publication number: 20200006394
    Abstract: A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is lower in crystallinity than the first region and the second region.
    Type: Application
    Filed: March 22, 2019
    Publication date: January 2, 2020
    Inventors: YUTA SUGAWARA, MASAKAZU TANAKA, NOBUTAKE NODERA, TAKAO MATSUMOTO