Patents by Inventor Takao Nishimura

Takao Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9268034
    Abstract: A nuclear reactor fuel integrity monitor includes: a ?-ray detector which detects ?-ray of a specific radionuclide of a subject measurement medium of a nuclear reactor; a sample container which retains the subject measurement medium therein and surrounds the circumference of the ?-ray detector; and a measurement control device which performs a control so that a predetermined amount of the subject measurement medium is introduced into the sample container and calculates a concentration of the specific radionuclide from ?-ray data per each unit time detected by the ?-ray detector and a volume of the subject measurement medium introduced into the sample container.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: February 23, 2016
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Takao Nishimura, Kenichiro Kino
  • Patent number: 9134433
    Abstract: A nuclear reactor fuel integrity monitor includes: a ?-ray detector which detects ?-ray of a specific radionuclide of a subject measurement medium of a nuclear reactor; a sample container which retains the subject measurement medium therein and surrounds the circumference of the ?-ray detector; and a measurement control device which performs a control so that a predetermined amount of the subject measurement medium is introduced into the sample container and calculates a concentration of the specific radionuclide from ?-ray data per each unit time detected by the ?-ray detector and a volume of the subject measurement medium introduced into the sample container.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: September 15, 2015
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Takao Nishimura, Kenichiro Kino
  • Patent number: 9076559
    Abstract: An object is to reduce radiation exposure in a nuclear plant. A nuclear plant 1 is a nuclear power generating plant where steam is generated by thermal energy generated by nuclear fission of a nuclear fuel 2C in a nuclear reactor 2, and a turbine 8 is driven by the steam to generate heat by a power generator 10. After a nuclear plant 1 is newly constructed, when a primary cooling system of the nuclear reactor 2 raises the temperature to around a power operation temperature for the first time, zinc is injected into a primary coolant C1 present in the primary cooling system by a zinc injector 20.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: July 7, 2015
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Takao Nishimura, Ryuji Umehara
  • Publication number: 20150115157
    Abstract: A nuclear reactor fuel integrity monitor includes: a ?-ray detector which detects ?-ray of a specific radionuclide of a subject measurement medium of a nuclear reactor; a sample container which retains the subject measurement medium therein and surrounds the circumference of the ?-ray detector; and a measurement control device which performs a control so that a predetermined amount of the subject measurement medium is introduced into the sample container and calculates a concentration of the specific radionuclide from ?-ray data per each unit time detected by the ?-ray detector and a volume of the subject measurement medium introduced into the sample container.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 30, 2015
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Takao Nishimura, Kenichiro Kino
  • Patent number: 9005082
    Abstract: An ECU increases an engine rotation speed when the ECU determines that an inclination angle of an uphill is larger than or equal to a predetermined value, an accelerator is off and a vehicle speed in a direction opposite to a travelling direction of a vehicle, indicated by a specified range, is increasing. Subsequently, the ECU acquires an engine stall predicted vehicle speed, and calculates a predetermined value used in an immediate engine stall determination condition from a current rate of increase per unit time of a turbine rotation speed. Then, the ECU determines that immediate engine stall determination is affirmative when a rotation speed difference between the engine rotation speed and the turbine rotation speed becomes smaller than the predetermined value, and executes engine stall prevention control.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: April 14, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Koji Okamura, Takao Nishimura, Masatomo Yoshihara, Fumikazu Satou
  • Publication number: 20140287873
    Abstract: An ECU increases an engine rotation speed when the ECU determines that an inclination angle of an uphill is larger than or equal to a predetermined value, an accelerator is off and a vehicle speed in a direction opposite to a travelling direction of a vehicle, indicated by a specified range, is increasing. Subsequently, the ECU acquires an engine stall predicted vehicle speed, and calculates a predetermined value used in an immediate engine stall determination condition from a current rate of increase per unit time of a turbine rotation speed. Then, the ECU determines that immediate engine stall determination is affirmative when a rotation speed difference between the engine rotation speed and the turbine rotation speed becomes smaller than the predetermined value, and executes engine stall prevention control.
    Type: Application
    Filed: October 26, 2012
    Publication date: September 25, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Koji Okamura, Takao Nishimura, Masatomo Yoshihara, Fumikazu Satou
  • Patent number: 8841776
    Abstract: In a semiconductor chip, a first semiconductor chip 21 is provided on a chip-mounting component 11, and bonding wires 36 connected to electrode pads 21E of the first semiconductor chip 21 are fixed by being covered with a first insulating adhesive 31. A second semiconductor chip 22 is mounted by being stacked on the first semiconductor chip 21, with the first insulating adhesive 31 therebetween. This structure can prevent problems such as breaking and short-circuits of bonding wires of the chip disposed directly on a substrate when another chip is mounted by being stacked.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Yoshiaki Narisawa
  • Patent number: 8810043
    Abstract: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Yoshikazu Kumagaya, Akira Takashima, Kouichi Nakamura, Kazuyuki Aiba
  • Patent number: 8748229
    Abstract: A semiconductor device includes a supporting board, a first semiconductor element mounted on a main surface of the supporting board; and an electronic component provided between the supporting board and the first semiconductor element; wherein the supporting board includes a concave part formed in a direction separated from the first semiconductor element; and at least a part of the electronic component is accommodated in the concave part.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: June 10, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Takayuki Norimatsu
  • Patent number: 8659168
    Abstract: A wiring board includes a main surface where an electronic component is mounted in a face-down manner so that a surface of the electronic component having plurality of external connecting terminals faces the main surface of the wiring board, the electronic component being fixed to the wiring board by an adhesive; an insulating layer formed on the main surface where the electronic component is mounted; an opening part formed in the insulating layer so that a plurality of adjacent wiring patterns are commonly and partially opened, the adjacent wiring patterns having electrodes where electrodes of the electronic component are connected; wherein an outer periphery of the opening part situated at a center side of the wiring board is formed in an oblique direction against extending directions of the wiring patterns.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: February 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Yoshikazu Kumagaya
  • Publication number: 20130134320
    Abstract: A nuclear reactor fuel integrity monitor includes: a ?-ray detector which detects ?-ray of a specific radionuclide of a subject measurement medium of a nuclear reactor; a sample container which retains the subject measurement medium therein and surrounds the circumference of the ?-ray detector; and a measurement control device which performs a control so that a predetermined amount of the subject measurement medium is introduced into the sample container and calculates a concentration of the specific radionuclide from ?-ray data per each unit time detected by the ?-ray detector and a volume of the subject measurement medium introduced into the sample container.
    Type: Application
    Filed: August 9, 2011
    Publication date: May 30, 2013
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Takao Nishimura, Kenichiro Kino
  • Patent number: 8404980
    Abstract: A relay board provided in a semiconductor device includes a first terminal, and a plurality of second terminals connecting to the first terminal by a wiring. The wiring connecting to the first terminal is split on the way so that the wiring connects to each of the second terminals.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: March 26, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Kouichi Nakamura
  • Publication number: 20120322202
    Abstract: A semiconductor device includes a supporting board, a first semiconductor element mounted on a main surface of the supporting board; and an electronic component provided between the supporting board and the first semiconductor element; wherein the supporting board includes a concave part formed in a direction separated from the first semiconductor element; and at least a part of the electronic component is accommodated in the concave part.
    Type: Application
    Filed: August 23, 2012
    Publication date: December 20, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takao Nishimura, Takayuki Norimatsu
  • Patent number: 8230590
    Abstract: A method for mounting electronic components includes a step of providing an adhesive on each of plural electronic component mounting parts on a wiring board; and a step of fixing one of the electronic components on each of the plural electronic component mounting parts via the adhesive. When the adhesive is provided on each of the plural electronic component mounting parts, the center of gravity of a volume of the adhesive provided on the mounting part where an Nth electronic component is to be mounted is shifted in a direction closer to the mounting part where an (N minus 1 or greater)th electronic component is provided neighboring and adjacent to the mounting part where the Nth electronic component is to be mounted.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: July 31, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Yoshiaki Narisawa
  • Patent number: 8216934
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Patent number: 8198728
    Abstract: A semiconductor device includes a supporting base whereupon an electrode terminal is placed; an intermediate member mounted on said supporting base; a semiconductor element, a portion thereof being supported with said intermediate member, and placed on said supporting base; and a convex-shaped member which corresponds to the electrode terminal of said semiconductor element and placed on said supporting base or said intermediate member; wherein the electrode terminal of said semiconductor element and the electrode terminal of said supporting base are connected with a bonding wire.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: June 12, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takao Nishimura
  • Patent number: 8134240
    Abstract: To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: March 13, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Yoshiaki Narisawa
  • Patent number: 8125789
    Abstract: A wiring substrate includes a plurality of electrode terminals, to which external connection terminals of an electronic component are coupled, arranged in a row on one principal surface thereof, wherein the electrode terminals each include: a first linear portion; a second linear portion extending from an end of the first linear portion in a direction different from a direction of the first linear portion; and a bent portion that is a part where the first linear portion and the second linear portion are connected.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: February 28, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takao Nishimura
  • Patent number: 8076769
    Abstract: A semiconductor device includes a semiconductor element; a plate member disposed opposite to an electronic-circuit forming portion of the semiconductor element; and an elastic body arranged in a compressed state between the semiconductor element and the plate member, wherein the elastic body includes at least one first protruding portion at one end in an extension direction of the elastic body, the first protruding portion being formed opposite to the electronic-circuit forming portion of the semiconductor element, and the semiconductor element and the plate member are fastened by an adhesive agent.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Yoshikazu Kumagaya
  • Patent number: 8076785
    Abstract: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Yoshikazu Kumagaya, Akira Takashima, Kouichi Nakamura, Kazuyuki Aiba