Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

Abstract: Embodiments of the present invention include a phase change memory (PCM) array. The PCM array may include a plurality of PCM cells. Each PCM cell in the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a global heater surrounding the plurality of PCM cells having a thermally conductive material contacting each of the plurality of PCM cells. The global heater may be configured to receive an electric signal to heat the plurality of PCM cells simultaneously.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level that includes a metal line, the metal line includes a bottom section having a first width, a middle section having a second width, and a top section having a third width, where the second width of the middle section is narrower than the first width of the bottom section and is narrower than the third width of the top section. A method of forming the semiconductor structure is also provided.

Abstract: A nanosheet field effect transistor (FET) comprises a diffusion region and a gate. The diffusion region connects to a backside power delivery network. The diffusion region is beneath the gate. The gate is in a first gate region. The gate comprises a first gate extension region that extends over the diffusion region.

Abstract: A semiconductor device includes a first stacked field-effect transistor structure having a first lower field-effect transistor device and a first upper field-effect transistor device. The semiconductor device also includes a second stacked field-effect transistor structure comprising a second lower field-effect transistor device and a second upper field-effect transistor device, where at least one of: the first lower field-effect transistor device includes a different number of channel layers than the second lower field-effect transistor device; and the first upper field-effect transistor device includes a different number of channel layers than the second upper field-effect transistor device.

Abstract: A resistive random access memory is provided including an asymmetrical or symmetrical bottom electrode which has an angled profile which forms an interface with a memory switching layer. The angled profile can include a slanted surface or one including a plurality of slanted surfaces that converge into a point. Bottom electrodes having such angled profiles provide more forming area, which can reduce forming voltage without area penalty. In some embodiments in which the slanted surfaces converge into a point, bottom electrodes having such an angled profile can also provide a more controlled area for the forming process to occur.

Abstract: A semiconductor structure includes a first nanosheet field-effect transistor device having a plurality of first nanosheet channel layers and a first interfacial layer surrounding each of the plurality of first nanosheet channel layers, the first interfacial layer having a first thickness, and a second nanosheet field-effect transistor device vertically stacked above the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device having a plurality of second nanosheet channel layers and a second interfacial layer surrounding each of the plurality of second nanosheet channel layers, the second interfacial layer having a second thickness greater than the first thickness. A distance between each of the plurality of second nanosheet channel layers is less than a distance between each of the plurality of first nanosheet channel layers.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include an NFET transistor with NFET nanosheets and a first workfunction setting metal that is pinched off within spaces between the NFET nanosheets and a PFET transistor with PFET nanosheets surrounded by a thin layer of a second workfunction setting metal. The semiconductor structure may also include a doped metal between the PFET nanosheets surrounded by a thin layer of a workfunction setting metal.

Abstract: A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end of the active region and a drain at a second end of the active region. The gate extends across the active region and includes at least one end extending past a corresponding edge of the active region by a sub-lithographic dimension.

Abstract: A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Abstract: A method for system authentication includes subjecting a system to a challenge. The method further includes receiving a response from the system. The received response is dependent upon a location of a filament in a resistive random-access memory device of the system. Additionally, the response is also a unique identifier.

Abstract: A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

Abstract: A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

Abstract: Embodiments of the invention include forming a first transistor having first nanosheets, first dipole gate dielectric material being formed around the first nanosheets. An aspect includes forming a second transistor comprising second nanosheets, second dipole gate dielectric material being formed around the second nanosheets, the first and second transistors being in a vertical stack, a first spacing between the first nanosheets being different from a second spacing between the second nanosheets. An aspect includes forming a workfunction metal stack having a first workfunction metal and a second workfunction metal, the first and second workfunction metals being formed between the first nanosheets, the first workfunction metal being formed to pinch off in the second spacing between the second nanosheets such that the second workfunction metal is absent in the second spacing between the second nanosheets.

Abstract: The present invention relates to a transparent polyimide film containing a polyimide and a phosphate ester. The content of the phosphate ester based on 100 parts by mass of the polyimide is 3 parts by mass or more, preferably 5 to 100 parts by mass. It is preferable to use a phosphate ester that has a high birefringence reduction effect and with which a decrease in the tensile modulus of the film is small. In production of the polyimide film, it is preferable to employ a method in which: a solvent-soluble polyimide resin and a phosphate ester are dissolved in an organic solvent exhibiting solubility with respect to the polyimide resin to prepare a polyimide solution; the polyimide solution is applied onto a substrate; and the organic solvent is removed.

Abstract: A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.

Abstract: Embodiments of the invention are directed to a structure that includes a resistive switching device (RSD). The RSD includes a first terminal having an outer sidewall surface; a second terminal; an active region having a switchable conduction state; and a first protective layer on the outer sidewall surface of the first terminal.

Abstract: Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

Abstract: A semiconductor device includes a substrate and a transistor positioned on the substrate. The transistor includes transistor includes a channel region, a shared gate region, and a source and drain region. The source and drain region includes a concave outer wall includes a concave outer wall. A method of manufacturing a semiconductor device includes providing a substrate and forming a plurality of transistor gate structures on the substrate. A source and drain region are formed and positioned adjacent the plurality of transistor gate structures. A concave wall is recessed into material of the source and drain region toward a centerline of the source and drain region.

Abstract: A semiconductor device includes a substrate and a plurality of stacked transistors positioned on the substrate. The transistors include a gate region and a source and drain proximate the gate region. The source and drain includes an overall region and an active region. A thickness of the active region is less than a thickness of the overall region.