Abstract: Embodiments of present invention provide a method of forming a resistive random-access memory (RRAM). The method includes forming a dielectric layer on top of a supporting structure, wherein the dielectric layer has a bottom electrode embedded therein; forming an oxide layer on top of the bottom electrode; treating the oxide layer in a plasma environment; forming a top electrode on top of the oxide layer; forming a first interlevel-dielectric (ILD) layer on top of the top electrode; forming a via contact and a first metal layer in the first ILD layer, wherein the first metal layer is in contact with the top electrode through the via contact; forming a capping layer on top of the first metal layer through a plasma-enhanced deposition process; and causing formation of one or more filaments in the oxide layer during the plasma-enhanced deposition process. A structure of the RRAM is also provided.

Abstract: An image forming apparatus including an image forming unit, a fixing unit, a reading unit, a reference member, and a controller is described. The image forming unit forms an image and a detection image on a sheet. The detection image is used for detecting geometric characteristics of an image to be formed on a sheet by the image forming unit. The fixing unit fixes the image and the detection image formed by the image forming unit on the sheet. The reading unit reads the detection image on the sheet. The controller adjusts geometric characteristics of the image to be formed on a sheet based on a reading result of the detection image by the reading unit, and controls the reading unit to read the reference member and executes shading correction based on a reading result of the reference member.

Abstract: An information processing apparatus disclosed has a controller configured to execute the processing of accepting a request for retrieving a target vehicle body unit that is laid at a specific place, selecting a chassis unit for retrieval from among chassis units in the state separated from any vehicle body unit, the chassis unit for retrieval being a chassis unit to be used to retrieve the target vehicle body unit, and sending a retrieval command to the chassis unit for retrieval, the retrieval command being a command to retrieve the target vehicle body unit.

Abstract: A non-volatile memory apparatus includes a first hydrogen reservoir, which is electrically conductive; a charge of hydrogen, which is captured in the first hydrogen reservoir; a dielectric layer that has a first side that is adjacent to the first hydrogen reservoir and a second side that is opposite from the first hydrogen reservoir; a second hydrogen reservoir that is adjacent to the second side of the dielectric layer, is electrically conductive, and has a side that is opposite from the dielectric layer; and a piezoelectric layer that is adjacent to the side of the second hydrogen reservoir and that has a side that is opposite from the second hydrogen reservoir.

Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment and a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring. A distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.

Abstract: A disclosed drum-type washing machine having a softening apparatus comprises: a cylindrical water tank accommodating laundry and having a rotating drum; a case for accommodating the water tank; and a softening apparatus having a hardness component remover for removing hardness components from washing water, and a regeneration agent accommodation unit spaced apart from the hardness component remover on opposite sides from a center of the tub, and for accommodating a regeneration agent that regenerates a function of the hardness component remover.

Abstract: A conveyance route switching mechanism and a paper sheet handling apparatus that includes the conveyance route switching mechanism include a driving source, a gate, a first gear, and an internal gear. The driving source includes a driving shaft. The gate includes a gate shaft, and a blade that is provided on the gate shaft, and switches conveyance routes of paper sheets. The first gear is provided on the gate shaft. The internal gear meshes with the first gear. According to rotation of the driving shaft, the gate shaft rotates on an axis of the gate shaft, and revolves with the driving shaft as a rotation center while the first gear meshes with the internal gear.

Abstract: A motor includes: a central shaft; a stator extending in an axial direction around the central shaft; a rotor facing an outer side in a radial direction of the stator and configured to rotate around the central shaft; a substrate located on one side in the axial direction with respect to the rotor and on which a rotation position detection circuit detecting a rotation position of the rotor is mounted; and a case located on one side in the axial direction with respect to the substrate and supporting the stator. The stator includes a restricting portion restricting a position in a circumferential direction of the substrate. The case includes a fixing portion fixing the substrate. The substrate includes a restricted portion whose position in the circumferential direction is restricted by the restricting portion, and a fixed portion fixed to the fixing portion.

Abstract: A control method for a fuel cell system, the fuel cell system including a hydrogen storage part and a fuel cell stack that generates electric power using hydrogen supplied from the hydrogen storage part, the fuel cell system being mounted on a towed portion of a moving body that includes the towed portion and a towing portion, the fuel cell system being electrically connected to the towing portion, the towing portion including a battery and a drive device performing driving in response to supply of electric power, the towed portion being towed by the towing portion, the control method includes: acquiring remaining amount information indicating a remaining amount of the battery, and starting supply of electric power to the towing portion when it is determined that the remaining amount of the battery is equal to or less than a threshold based on the remaining amount information.

Abstract: Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

Abstract: A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

Abstract: An embodiment of the invention may include a semiconductor structure, method of use and method of manufacture. The structure may include a heating element located underneath a temperature-controlled portion of the device. A method of operating the semiconductor device may include providing current to a thin film heater located beneath a temperature-controlled region of the semiconductor device. The method may include performing temperature dependent operations in the temperature-controlled region.

Abstract: A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Abstract: A semiconductor device including an interleaved/nested structure of subtractive interconnects and damascene interconnects. The semiconductor device includes a subtractive-etched interconnect wiring level having subtractive interconnects and a damascene interconnect wiring level having damascene interconnects. The subtractive-etched interconnect wiring level includes first electrodes that have a first potential second electrodes that have a second potential different from the first potential, with the second electrodes generated to interleave the first electrodes. The semiconductor also includes a damascene interconnect wiring level that includes other first electrodes having the first potential, and other second electrodes having the second potential. In the damascene interconnect wiring level, the other second electrodes are also interleaved by the other first electrodes.

Abstract: An image forming apparatus including an image forming unit, a fixing unit, a reading unit, a reference member, and a controller is described. The image forming unit forms an image and a detection image on a sheet. The detection image is used for detecting geometric characteristics of an image to be formed on a sheet by the image forming unit. The fixing unit fixes the image and the detection image formed by the image forming unit on the sheet. The reading unit reads the detection image on the sheet. The controller adjusts geometric characteristics of the image to be formed on a sheet based on a reading result of the detection image by the reading unit, and controls the reading unit to read the reference member and executes shading correction based on a reading result of the reference member.

Abstract: A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.

Abstract: A grain-boundary self-aligned resistive memory structure is provided enabling the closely-packed formation of multiple, oxide-based, ReRAM elements in parallel, each with its own compliance resistor. The structure is capable of forming multiple filaments, one per element, with the aim of reducing the variability in the composite ReRAM cell.

Abstract: To limit resistance variability across a resistive random-access memory (RRAM) call, the disclosure includes an RRAM cell with a resistance spreading layer within the RRAM cell between the top and bottom electrodes of the RRAM cell. The resistance spreading layer is in series with and has no impedance with a filament forming layer of the RRAM cell. The resistance spreading layer may be below the filament forming layer or the resistance spreading layer may be above the filament forming layer. The resistance spreading layer may further be in series with and has no impedance with the bottom electrode or the top electrode.