Patents by Inventor Takashi Ando

Takashi Ando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190319095
    Abstract: A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET S/D structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 17, 2019
    Inventors: Jingyun Zhang, Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek
  • Publication number: 20190318966
    Abstract: A integrated circuit including an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening, a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening, a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer, and a bulk fill material above and in direct contact with the shared work function metal.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 10442797
    Abstract: The present disclosure provides novel compounds or salts thereof, or crystals of the compounds or the salts, which inhibit Axl and are useful in the treatment of a disease caused by hyperfunction of Axl, the treatment of a disease associated with hyperfunction of Axl, and/or the treatment of a disease involving hyperfunction of Axl.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: October 15, 2019
    Assignee: DAIICHI SANKYO COMPANY, LIMITED
    Inventors: Noriyasu Haginoya, Takashi Suzuki, Miho Hayakawa, Masahiro Ota, Tomoharu Tsukada, Katsuhiro Kobayashi, Yosuke Ando, Takeshi Jimbo, Koichi Nakamura
  • Publication number: 20190311958
    Abstract: A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Inventors: Choonghyun Lee, Pouya Hashemi, Takashi Ando
  • Publication number: 20190312120
    Abstract: A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels, interfacial layers formed around the first channels, and dielectric material including first and second portions having respective thicknesses formed on the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels, the interfacial layers formed around the second channels, and the dielectric material formed on the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.
    Type: Application
    Filed: April 6, 2018
    Publication date: October 10, 2019
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee
  • Publication number: 20190305076
    Abstract: A method is presented for forming a stacked metal-insular-metal (MIM) capacitor with self-aligned contact. The method includes forming a first electrode plate over a first interlayer dielectric (ILD), forming a first spacer adjacent the first electrode plate, forming a first insulating layer over the first electrode plate, forming a second electrode plate over the first insulating layer, and forming a second spacer adjacent the second electrode plate and the first insulating layer. The method further includes forming a second insulating layer over the second electrode plate, forming a third electrode plate over the second insulating layer, forming a third spacer adjacent the third electrode plate and the second insulating layer, and forming a second ILD over the third electrode plate. The method also includes forming a first via through the second ILD and directly contacting the second spacer such to prevent the first via from contacting the second electrode plate.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Inventors: Takashi Ando, Robert Allen Groves, Hemanth Jagannathan, Lawrence A. Clevenger, Griselda Bonilla
  • Publication number: 20190295949
    Abstract: A semiconductor device including an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and including an epitaxial growth, the highly doped fuse region implanted with ions.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 26, 2019
    Inventors: Alexander REZNICEK, Pouya HASHEMI, Miaomiao WANG, Takashi ANDO
  • Publication number: 20190295950
    Abstract: A semiconductor device comprising an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and comprising an epitaxial growth, the highly doped fuse region implanted with ions.
    Type: Application
    Filed: May 14, 2019
    Publication date: September 26, 2019
    Inventors: Alexander REZNICEK, Pouya HASHEMI, Miaomiao WANG, Takashi ANDO
  • Publication number: 20190296106
    Abstract: A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Takashi Ando, Pouya Hashemi, Mahmoud Khojasteh, Alexander Reznicek
  • Publication number: 20190281820
    Abstract: An antibacterial fiber that includes a charge generation member shaped in a fibrous form and that generates charges sufficient to suppress the proliferation of a bacillus by input of external energy, and a water-resistant member that covers the charge generation member.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Inventors: Kentaro USUI, Takashi KIHARA, Yoshihiro YAMAGUCHI, Shozo OTERA, Fumiya ISONO, Masamichi ANDO, Yutaka ISHIURA
  • Publication number: 20190280107
    Abstract: A method of forming a semiconductor device that includes forming a stack of nanosheets composed of a semiconductor material; and forming a sacrificial layer of a work function adjusting material on the semiconductor material of the stack of nanosheets. In a following step, the work function adjusting material is mixed into the semiconductor material on at least a channel surface of nanosheets. The sacrificial layer is removed. An interfacial oxide layer is formed including elements from the semiconductor material and the work function adjusting layer on said at least the channel surface of the stack of nanosheets. A gate structure including a gate dielectric is formed on the interfacial oxide that is present on the channel surface of the nanosheets.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: Takashi Ando, Choonghyun Lee, Pouya Hashemi
  • Publication number: 20190280033
    Abstract: An image sensor includes: a first pixel including a first micro lens, a first photoelectric conversion unit that photoelectrically converts light that has passed through the first micro lens, and a reflective unit that reflects light that has passed through the first photoelectric conversion unit back to the first photoelectric conversion unit; and a second pixel including a second micro lens and a second photoelectric conversion unit that photoelectrically converts light that has passed through the second micro lens, wherein: positions of condensation of incident light in the first pixel and the second pixel are different.
    Type: Application
    Filed: September 20, 2017
    Publication date: September 12, 2019
    Applicant: NIKON CORPORATION
    Inventors: Shutaro KATO, Toru TAKAGI, Satoshi NAKAYAMA, Takashi SEO, Ryoji ANDO
  • Publication number: 20190273205
    Abstract: A method is presented for increasing resistance of a resistive random access memory (ReRAM) device. The method includes forming a first electrode, forming an insulating layer over the first electrode, and forming a second electrode over the insulating layer, the second electrode constructed by depositing a stoichiometric oxygen barrier layer and depositing an oxidized conducting layer directly over the stoichiometric oxygen barrier layer to create a high-resistance conductive path between the first and second electrodes of the ReRAM device.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 5, 2019
    Inventors: Takashi Ando, Eduard A. Cartier, Seyoung Kim, John Bruley
  • Publication number: 20190273106
    Abstract: An image sensor includes a plurality of pixels each including: a photoelectric conversion unit that photoelectrically converts incident light and generates electric charge; a reflective unit that reflects light that has passed through the photoelectric conversion unit back to the photoelectric conversion unit; and an output unit that outputs electric charge generated by the photoelectric conversion unit, wherein: an area of the reflective unit possessed by each of the plurality of pixels varies.
    Type: Application
    Filed: September 21, 2017
    Publication date: September 5, 2019
    Applicant: NIKON CORPORATION
    Inventors: Shutaro KATO, Toru TAKAGI, Satoshi NAKAYAMA, Takashi SEO, Ryoji ANDO
  • Patent number: 10405429
    Abstract: A transformer integrated type printed circuit board includes: a transformer including a core, a primary winding wire, and a secondary winding wire; and a printed circuit board including a surface layer and an internal layer in which wiring patterns are respectively formed, and having a plurality of insertion portions into which a plurality of leg portions of the core are respectively inserted. The primary winding wire is disposed in the surface layer of the printed circuit board so as to be wound between the leg portions, and the secondary winding wire is disposed in the internal layer of the printed circuit board so as to be wound between the leg portions. The primary winding wire is small in number of windings, is large in width, and is large in thickness, in comparison with the secondary winding wire.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 3, 2019
    Assignee: OMRON Corporation
    Inventors: Masanori Ando, Takashi Yamaguchi
  • Patent number: 10401986
    Abstract: A pointer includes: a pointer tip having a tip configured to point a position; a transmitter configured to emit a signal from the pointer tip; and a main body connected to the pointer tip. The main body includes: an exterior housing forming an exterior; a detector configured to detect displacement of the exterior housing and output a detection signal; and a controller configured to change an operation state of the pointer in accordance with the detection signal. The detector includes: a detection device provided on an inner surface of the exterior housing and configured to detect the displacement; and a signal outputter configured to output the detection signal in the case where the detection device detects the displacement.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: September 3, 2019
    Assignees: SEIKO EPSON CORPORATION, MURATA MANUFACTURING CO., LTD.
    Inventors: Daigo Yamano, Shingo Wakimoto, Takashi Kihara, Masamichi Ando, Hiroaki Kitada, Jun Endo, Yoshihiro Yamaguchi
  • Publication number: 20190267243
    Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventors: Takashi Ando, Robert H. Dennard, Martin M. Frank
  • Publication number: 20190268543
    Abstract: An image sensor includes pixels arranged in a first direction. Each of first and second pixels has a photoelectric conversion unit converting incident light and generating electric charge, a reflective unit reflecting light, and an output unit. In a plane intersecting the incident light direction, the first pixel reflective unit is in a region more toward the first direction than the first pixel photoelectric conversion unit center. In a plane intersecting the incident light direction, the second pixel reflective unit is in a region more toward the direction opposite to the first direction than the second pixel photoelectric conversion unit center. First and second pixel output unit portions are respectively upon optical paths along which light having passed through the first and second pixel photoelectric conversion units are incident upon the first and second pixel reflective units.
    Type: Application
    Filed: September 19, 2017
    Publication date: August 29, 2019
    Applicant: NIKON CORPORATION
    Inventors: Shutaro KATO, Toru TAKAGI, Satoshi NAKAYAMA, Takashi SEO, Ryoji ANDO
  • Patent number: 10396146
    Abstract: Methods of forming capacitors include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Hemanth Jagannathan, Paul C. Jamison, John Rozen
  • Patent number: 10395993
    Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui