Abstract: A physical unclonable function device includes alternating regions of programable material and electrically conductive regions. The regions of programable material are configured to switch resistance upon receiving an electric pulse. An electric pulse applied between two outer electrically conductive regions of the alternating regions will switch the resistance of at least one region of programmable material. The alternating regions may include a plurality of the electrically conducting regions and a region of the programable material disposed between each of the plurality of electrically conductive regions. The resistance of each of the regions of programable material is selectively variable in at least a portion thereof as a result of the electric pulse flowing therethrough. The resistance value of the programable material region may be a readable value as a state of the device. The regions of programmable material may be formed of a phase change material or an oxide.

Abstract: Embodiments of process flows and methods are provided for forming a resistive switching random access memory (ReRAM). More specifically, process flows and methods are provided for reducing the forming voltage needed to form a conductive path in the ReRAM cells. A wide variety of plasma doping processes are used to introduce a plurality of different dopants into a metal-oxide dielectric film. By utilizing at least two different dopants, the plasma doping processes described herein reduce the forming voltage of the subsequently formed ReRAM cell compared to conventional processes that use only one dopant. In some embodiments, the forming voltage may be further reduced by applying a bias power during the plasma doping process, wherein the bias power is preselected to increase the number of ions introduced into the metal-oxide dielectric film during the plasma doping process.

Abstract: Embodiments of the invention are directed to a configuration of nanosheet FET devices in a first region of a substrate. Each of the nanosheet FET devices in the first region includes a first channel nanosheet, a second channel nanosheet over the first channel nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure. The first gate structure includes a doped region, and the second gate structure includes a doped region. At least a portion of the pinch off area is undoped.

Abstract: A method of manufacturing a low program voltage flash memory cell with an embedded heater in the control gate creates, on a common device substrate, a conventional flash memory cell in a conventional flash memory area (CFMA), and a neuromorphic computing memory cell in a neuromorphic computing memory area (NCMA). The method comprises providing a flash memory stack in both the CFMA and the NCMA, depositing a heater on top of the flash memory stack in the NCMA without depositing a heater on top of the flash memory stack in the CFMA.

Abstract: A semiconductor device includes a semiconductor substrate and a field effect transistor disposed on the semiconductor substrate. The field effect transistor includes a vertical fin defining a longitudinal length along a first axis, a width along a second axis and a vertical height along a third axis. The vertical fin includes source and drain regions separated by a gate region and a gate structure over the gate region. The gate structure includes a dipole layer and a gate electrode layer over the dipole layer. A first longitudinal section of the gate structure includes the dipole layer and a second longitudinal section of the gate structure is devoid of the dipole layer.

Abstract: Resistive memory devices are provided which are configured to mitigate resistance drift. A device comprises a phase-change element, a resistive liner, a first electrode, a second electrode, and a third electrode. The resistive liner is disposed in contact with a first surface of the phase-change element. The first electrode is coupled to a first end portion of the resistive liner. The second electrode is coupled to a second end portion of the resistive liner. The third electrode is coupled to the first surface of the phase-change element.

Abstract: Methods and structures for fabricating a semiconductor device that includes a reduced programming current phase change memory (PCM) are provided. The method includes forming a bottom electrode. The method further includes forming a PCM and forming a conductive bridge filament in a dielectric to serve as a heater for the PCM. The method also includes forming a top electrode.

Abstract: Techniques for fabricating semiconductor structures and devices with stacked structures having embedded capacitors are disclosed. In one example, a semiconductor structure includes a substrate having a first region and a second region. The semiconductor structure further includes a capacitor structure disposed in the second region of the substrate. The capacitor structure includes a capacitor conductor and a dielectric insulator disposed between the capacitor conductor and the substrate. The semiconductor structure further includes a stacked device disposed on the first region of the substrate. The stacked device includes a first transistor and a second transistor. At least a portion of the second transistor is disposed under at least a portion of the first transistor. The first transistor and the second transistor are each coupled to the capacitor conductor.

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack on a substrate. The nanosheet stack includes an alternating sequence of sacrificial nanosheets and channel nanosheets. The sacrificial nanosheets include second nanosheets located between first nanosheets and third nanosheets. The first nanosheets and the third nanosheets have a first germanium concentration that is lower than a second germanium concentration of the second nanosheets. The sacrificial nanosheets are selectively etched and the lower first germanium concentration causes the first nanosheets and the third nanosheets to be etched slower than the second nanosheets creating an indentation region on opposing sides of the nanosheet stack. The indentation region has a narrowing shape towards remaining second nanosheets of the sacrificial nanosheets.

Abstract: A unit structure of non-volatile memory is provided. The unit structure includes a substrate, an n-type ferroelectric field effect transistor (FeFET) and a p-type FeFET disposed on the substrate, first circuitry by which sources of the n-type FeFET and the p-type FeFET are electrically coupled in parallel downstream from a common terminal and second circuitry by which top electrodes of the n-type FeFET and the p-type FeFET are electrically coupled in parallel upstream of a common terminal.

Abstract: A resistive memory device with an embedded shoulder pulled sidewall spacer and method of forming. The method includes providing a patterned film stack containing a lower electrode layer, a dielectric filament layer on the lower electrode layer, and an upper electrode layer on the dielectric filament layer, depositing a conformal cap layer on the patterned film stack, dry etching the conformal cap layer to form a sidewall spacer on sidewalls of the patterned film stack, where a top of the sidewall spacer is recessed to below a top of the upper electrode layer by the dry etching. The method further includes encapsulating the patterned film stack in an isolation layer, and etching the isolation layer to expose the upper electrode layer without exposing the sidewall spacer.

Abstract: A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.

Abstract: A solid-state switch structure including a first solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following a first type programming pulse and a low electrical resistance obtained following a second type programming pulse, a second solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following said second type programming pulse and a low electrical resistance obtained following said first type programming pulse, a first contact made to a first end of said first solid-state material, a second contact made to a first end of said second solid-state material, a third contact made to a second end of said first solid-state material and to a second end of said second solid-state material.

Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.

Abstract: A resistive switching memory stack, comprised of a bottom electrode, an oxide layer located on the bottom electrode; and a top electrode located on the oxide layer. The top electrode is comprised of a first layer, an intermediate layer located directly on the first layer, and a top layer located on top of the intermediate layer. Wherein the intermediate layer is comprised of a doped carbide active layer.

Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Abstract: Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.

Abstract: A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.

Abstract: A semiconductor device includes a substrate material with a semiconductor material with a predetermined crystal orientation, a gate stack having a plurality of nanosheet channel layers, each nanosheet channel layer being controlled by metal gate layers located above and below the nanosheet channel layer, each nanosheet channel layer having the same semiconductor material and crystal orientation as that of the substrate, and a source/drain region on opposite sides of the gate stack. Each source/drain region includes bridging structures respectively connected to each nanosheet channel layer.