Abstract: A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.

Abstract: Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.

Abstract: A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

Abstract: A tunable nonvolatile resistive element, wherein the device conductance is modulated by changing the length of a contact between a phase change material and a resistive liner. By choosing the contact length to be less than the transfer length a linear modulation of the conductance is obtained.

Abstract: A semiconductor structure includes a semiconductor structure. The semiconductor structure may include a top transistor, a bottom transistor stacked below the top transistor, a back-end-of-line (BEOL) memory device electrically coupled to and above the top transistor, and a backside memory device electrically coupled to and below the bottom transistor.

Abstract: A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: Embodiments are disclosed for a field effect transistor (FET) device. The FET device includes a semiconductor channel. Additionally, the FET device includes a first gate dielectric in contact with the semiconductor channel. Further, the FET device includes a metal-insulator-metal (MIM) structure. The MIM structure includes a liner comprising a first metal, an insulator, and a second metal. The first metal is in contact with the first gate dielectric. Additionally, the insulator is in contact with the first metal and the second metal. Further, the FET device includes a floating gate. The floating gate includes the first metal and an extension. Additionally, the extension is disposed to one side of the MIM structure, and includes a surface for sensing a sample in contact with the surface.

Abstract: A memory structure that includes a dielectric stack of a ferroelectric dielectric layer and a paraelectric dielectric layer. At least the ferroelectric dielectric layer produces a negative capacitance to amplify an applied voltage. A thickness of the ferroelectric dielectric layer and the paraelectric dielectric layer results in simultaneous breakdown of a dielectric material in each of the ferroelectric dielectric layer and the paraelectric dielectric layer for the formation of conductive filaments upon being exposed to an electric field produced by the applied voltage amplified by the negative capacitance. The memory structure also includes a first electrode at a first end of the dielectric stack, and a second electrode at a second end of the dielectric stack. The applied voltage is applied to the memory structure through at least one of the first electrode and the second electrode.

Abstract: An array of resistive memory elements can be configured to store a plurality of values representing elements of a matrix. The array of resistive memory elements can be further configured to, responsive to an input vector being provided to the resistive memory elements, output a resulting vector representing a matrix multiplication of the matrix and the input vector, where the input vector includes a summation of a plurality of orthogonal vectors. A plurality of matched filters can be connected to outputs of the resistive memory elements, where each of the plurality of matched filters is configured to extract from the resulting vector a matrix multiplication result corresponding to a matrix multiplication of the matrix with one of the orthogonal vectors for which the respective matched filter is matched.

Abstract: In an approach to a implementing a PUF based on a PCM array, for each PCM device in an array of PCM devices, the PCM device is reset to an initial state. A first conductance of the PCM device is measured. A predetermined number of partial set pulses is applied to the PCM device. A second conductance of the PCM device is measured. Responsive to determining that the second conductance is greater than the first conductance multiplied by a factor, a PUF value of the PCM device is set to logical “1”. Responsive to determining that the second conductance is less than the first conductance multiplied by a factor, a PUF value of the PCM device is set to logical “0”. The PUF value of the PCM device is added to an overall PUF string for the array of PCM devices.

Abstract: An apparatus comprises a phase-change material, a first electrode at a first end of the phase-change material, a second electrode at a second end of the phase-change material, and a heating element coupled to a least a given portion of the phase-change material between the first end and the second end. The apparatus also comprises a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

Abstract: A disclosed drum-type washing machine having a softening apparatus comprises: a cylindrical water tank accommodating laundry and having a rotating drum; a case for accommodating the water tank; and a softening apparatus having a hardness component remover for removing hardness components from washing water, and a regeneration agent accommodation unit spaced apart from the hardness component remover on opposite sides from a center of the tub, and for accommodating a regeneration agent that regenerates a function of the hardness component remover.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment and a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring. A distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.

Abstract: A method of manufacturing a resistive random access memory (RRAM) cell includes forming an electrode, and forming an insulator on the electrode, the insulator having a pore and an insulator surface. The method also includes forming a dielectric material on the insulator and the electrode using an atomic layer deposition (ALD) process such that a seam exists in the dielectric material, and forming another electrode on the dielectric material.

Abstract: A circuit structure includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is connected to a wordline, and the first source electrode and the second source electrode are connected to a bitline. The first drain electrode is connected to the second gate electrode and the second drain electrode is connected to a bias line. A weight synapse structure is constructed by combining two circuit structures. A plurality of weight synapse structures are incorporated into a crossbar array.

Abstract: Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current can flow through one of the two non-volatile memory devices depending on the voltage level driving the current. To control which branch an input current flows through, each of the two non-volatile memory devices can be connected to a circuit element that can function as a switch, for example, a diode such as a semiconductor diode, a transistor, or another circuit element. Such apparatus can implement an analog memory-based activation function, for example, for an analog memory-based artificial neural network.

Abstract: A logic cell includes a first trench capacitor disposed between and connecting a topside metal layer to a backside metal layer. The first trench capacitor includes an outer plate, connected to a first power rail on the backside metal layer, an inner plate, connected to a second power rail on backside metal layer, and an insulating layer separating the inner plate from the outer plate.

Abstract: A memory device including a trench to a first electrically conductive structure; a first electrode of a conformal electrically conductive material contained within the trench in electrical communication with the first electrically conductive structure and is present on sidewalls of the trench; a switching layer is present in the trench on the first electrode and extends outside the trench; and a second electrode present on the switching layer overfilling the trench. The memory device also includes a contact positioned on a portion of the second electrode that is overfilling the trench to provide that the contact is horizontally offset from the first electrode that is present in the trench.