Patents by Inventor Takashi Hashimoto

Takashi Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10625314
    Abstract: A cleaning water feeding tool having a pipe structure to feed cleaning water to a water sprinkling cleaning device which has both end portions rotatably supported by a rotary base laid between a pair of rotary support parts disposed opposite to each other on a basket-shaped base, and includes the rotary head rotates with respect to the rotary base, and the rotary base rotates with respect to the basket-shaped base, including a horizontal portion that has a tip end portion connected to the cleaning water supply port and extends approximately horizontally in a state where a rotary shaft of the rotary base is disposed approximately horizontally, a straight portion that extends upward from the horizontal portion; and a hard material that configures or covers at least a portion receiving the cleaning water jetted from the water jet part of the straight portion.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: April 21, 2020
    Assignee: TRINITY INDUSTRIAL CORPORATION
    Inventor: Takashi Hashimoto
  • Publication number: 20200107020
    Abstract: An encoder includes processing circuitry and memory. Using the memory, the processing circuitry: encodes and reconstructs an image to generate a reconstructed image; determines, according to a characteristic of a block in the reconstructed image, an interpolation method for interpolating pixels located outside a referable region including the block; interpolates the pixels located outside the referable region, using the interpolation method determined; and applies a filter to the block using the pixels interpolated.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Inventors: Ryuichi KANOH, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Takashi HASHIMOTO
  • Publication number: 20200099952
    Abstract: Provided is an encoder that achieves further improvement. The encoder includes processing circuitry and memory. Using the memory, the processing circuitry: obtains two prediction images from two reference pictures; derives a luminance gradient value of each pixel position in each of the two prediction images; derives a luminance local motion estimation value of each pixel position in a current block; generates a luminance final prediction image using a luminance value and the luminance gradient value in each of the two prediction images, and the luminance local motion estimation value of the current block; and generates a chrominance final prediction image using at least one of the luminance gradient value of each of the two prediction images or the luminance local motion estimation value of the current block, and chrominance of each of the two prediction images.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Ryuichi KANOH, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Takashi HASHIMOTO
  • Publication number: 20200051905
    Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Yoshiyuki KAWASHIMA, Takashi HASHIMOTO
  • Publication number: 20200053386
    Abstract: An encoder includes memory and circuitry. The circuitry (i) encodes first control information indicating one mode, (ii) encodes second control information indicating whether it is possible to perform the motion compensation in a unit of a sub-block, (iii) derives the motion vector of the block in the one mode, (iv) determines whether to perform the motion compensation in the unit of the sub-block or the motion compensation in a unit of the block, (v) derives a motion vector of the sub-block and performs the motion compensation in the unit of the sub-block using the motion vector of the sub-block when determining to perform the motion compensation in the unit of the sub-block, and (vi) performs the motion compensation in the unit of the block using the motion vector of the block when determining to perform the motion compensation in the unit of the block.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Takashi HASHIMOTO
  • Publication number: 20200053382
    Abstract: An encoder that; obtains two prediction images by performing motion compensation using two motion vectors; obtains a gradient value of each of pixels included in the two prediction images; derives a local motion estimation value for each of sub-blocks based on the pixel value and the gradient value of each of the pixels, the sub-blocks being obtained by partitioning the current block; and generates a final prediction image for the current block using the pixel value and the gradient value of each of the pixels, and the local motion estimation value derived for each of the sub-blocks. Each of the pixels in the two prediction images is interpolated with sub-pixel accuracy, and a reference range for the interpolation is included in a normal reference range that is referred to for motion compensation for the current block in normal inter prediction performed without using the local motion estimation value.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Takashi HASHIMOTO
  • Publication number: 20200045329
    Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Inventors: Takashi HASHIMOTO, Takahiro NISHI, Tadamasa TOMA, Kiyofumi ABE, Ryuichi KANOH
  • Publication number: 20200033402
    Abstract: A load board to which a socket is mounted is electrically connected to a tester. The load board includes a first optical communication unit capable of transmitting and/or receiving signals by optical wireless communication with an electronic component handling apparatus that presses a DUT against the socket.
    Type: Application
    Filed: March 12, 2019
    Publication date: January 30, 2020
    Applicant: ADVANTEST Corporation
    Inventors: Takashi Hashimoto, Keishi Oku, Hiroaki Takeuchi, Takatoshi Yoshino
  • Publication number: 20200015511
    Abstract: Two genes, A622 and NBB1, can be influenced to achieve a decrease of nicotinic alkaloid levels in plants. In particular, suppression of one or both of A622 and NBB1 may be used to decrease nicotine in tobacco plants.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 16, 2020
    Applicant: 22nd Century Limited, LLC
    Inventors: Takashi Hashimoto, Akira Kato
  • Patent number: 10522978
    Abstract: In an ignition plug, since a ground electrode is formed in a thin-rod-shape or a mesh-like shape, sufficiently strong radicals are locally generated by a barrier discharge, an anti-inflammation effect by the electrode is small, and the growth of a flame is hardly hindered. Furthermore, by making the thickness dimension of a second dielectric facing a discharge region uniform, the barrier discharge is spread over the surface of the second dielectric, the generation of the radicals is maintained, and combustibility after ignition is promoted. Furthermore, because an end portion of a high voltage electrode and a ground electrode are disposed to face each other within a combustion chamber, a fuel gas introduced into the combustion chamber is liable to flow into the discharge region, and is easily ignited by the radicals generated due to the discharge.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: December 31, 2019
    Assignees: Mitsubishi Electric Corporation, NGK SPARK PLUG CO., LTD.
    Inventors: Taichiro Tamida, Takahiro Inoue, Takashi Hashimoto, Akira Nakagawa, Tomokazu Sakashita, Takayoshi Nagai, Kimihiko Tanaya, Hiroyuki Kameda, Yuichi Yamada, Kenji Ban
  • Publication number: 20190363095
    Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 28, 2019
    Inventors: Yuto OMIZU, Takashi HASHIMOTO, Hideaki YAMAKOSHI
  • Patent number: 10490496
    Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: November 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 10483273
    Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Yamakoshi, Takashi Hashimoto, Shinichiro Abe, Yuto Omizu
  • Publication number: 20190348429
    Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventors: Hideaki YAMAKOSHI, Takashi HASHIMOTO, Shinichiro ABE, Yuto OMIZU
  • Patent number: 10473357
    Abstract: A flow-straightening device at a coupling portion between: an air supply chamber adjacent to a coating chamber and supplying air to the coating chamber via a filter provided at a boundary wall between the air supply chamber and the coating chamber; and an air supply duct supplying air to the air supply chamber in a direction along the boundary wall. When a direction parallel to the boundary wall and perpendicular to the air supply chamber width direction is an air supply chamber depth direction; and a direction perpendicular to the boundary wall is an air supply chamber thickness direction, the device includes a plurality of fins arranged in the air supply chamber width direction and the air supply chamber depth direction and juxtaposed to each other to be spaced apart from each other in the chamber thickness direction.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: November 12, 2019
    Assignee: TRINITY INDUSTRIAL CORPORATION
    Inventors: Yoshifumi Takagi, Masayuki Miyake, Takashi Hashimoto
  • Patent number: 10436127
    Abstract: A change amount per unit time of an engine output command for controlling engine output of an internal combustion engine is calculated as an engine output increasing rate, and a power supply device is controlled so that power corresponding to the calculated engine output increasing rate is supplied to a combustion promoter generation device. The combustion promoter generation device generates a combustion promoter through the power supplied from the power supply device to supply the combustion promoter to a combustion chamber of the internal combustion engine, and a generation amount of the combustion promoter increases as the supplied power increases. In this manner, the generation amount of the combustion promoter is adjusted.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 8, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takahiro Inoue, Taichiro Tamida, Takashi Hashimoto, Noboru Wada, Akira Nakagawa, Tomokazu Sakashita, Tetsuya Honda
  • Publication number: 20190279998
    Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.
    Type: Application
    Filed: February 19, 2019
    Publication date: September 12, 2019
    Inventors: Hideaki YAMAKOSHI, Shinichiro ABE, Takashi HASHIMOTO, Yuto OMIZU
  • Patent number: 10388660
    Abstract: A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.
    Type: Grant
    Filed: October 29, 2017
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 10368573
    Abstract: Two genes, A622 and NBB1, can be influenced to achieve a decrease of nicotinic alkaloid levels in plants. In particular, suppression of one or both of A622 and NBB1 may be used to decrease nicotine in tobacco plants.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 6, 2019
    Assignee: 22nd Century Limited, LLC
    Inventors: Takashi Hashimoto, Akira Kato
  • Publication number: 20190238855
    Abstract: Provided is an image encoding method which inhibits deterioration in processing performance for encoding while improving transmission efficiency. The image encoding method is for generating a bitstream by encoding a picture, and includes: sequentially encoding blocks included in the picture; deriving an encoding amount of a slice segment each time one of the blocks is encoded as a current block, the slice segment including the current block; determining whether the encoding amount derived is at least a threshold; and setting end information indicating an end of the slice segment in a position in the bitstream when the encoding amount is determined to be at least the threshold, the position corresponding to the current block encoded.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Toshihiko KUSAKABE, Shinji KITAMURA, Kiyofumi ABE, Hideyuki OHGOSE, Takashi HASHIMOTO