Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

Abstract: According to one embodiment, a memory system includes a plurality of nonvolatile memories, a generator which generates a select information, an issuing unit which issues a select command including the select information, a decoder which decodes the select information and the select command, and a selector which selects one of the plurality of nonvolatile memories on the basis of the decoding result from the decoder.

Abstract: According to one embodiment, a controller includes a first command queuing part corresponding to a first bank, the first command queuing part queuing a first command, a second command queuing part corresponding to a second bank, the second command queuing part queuing a second command, and a command execution control part which is configured to generate a first sub-command sequence based on a group of commands in the first command, generate a second sub-command sequence based on a group of commands in the second command, and determine whether or not to execute the first and second sub-command sequences in parallel as an interleave operation between the first and second banks, by comparing an additional value of a first numeric converted parameter of the first sub-command sequence and a second numeric converted parameter of the second sub-command sequence with a threshold data.

Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

Abstract: According to one embodiment, a controller includes a first command queuing part corresponding to a first bank, the first command queuing part queuing a first command, a second command queuing part corresponding to a second bank, the second command queuing part queuing a second command, and a command execution control part which is configured to generate a first sub-command sequence based on a group of commands in the first command, generate a second sub-command sequence based on a group of commands in the second command, and determine whether or not to execute the first and second sub-command sequences in parallel as an interleave operation between the first and second banks, by comparing an additional value of a first numeric converted parameter of the first sub-command sequence and a second numeric converted parameter of the second sub-command sequence with a threshold data.

Abstract: According to one embodiment, a controller includes a first command queuing part corresponding to a first bank, the first command queuing part queuing commands, a second command queuing part corresponding to a second bank, the second command queuing part queuing commands, and a bank control part which is configured to generate a first bound command by binding at least two commands in the first command queuing part, generate a second bound command by binding at least two commands in the second command queuing part, transfer the first bound command as an unit of an interleave operation between the first and second banks to the first bank, and transfer the second bound command as an unit of the interleave operation to the second bank.

Abstract: A piston of an internal combustion engine includes a crown portion; a pair of thrust-side and counter-thrust-side skirt portions; and a pair of apron portions connecting the thrust-side skirt portion with the counter-thrust-side skirt portion. Each of the pair of apron portions includes an upper end wall connected with the crown portion, and a pin boss portion supporting a piston pin. A reverse-surface-side portion of the crown portion is formed with a hollow portion extending along an outer surface of the upper end wall of the apron portion. The upper end wall of the apron portion includes a bending portion between an outside surface of the pin boss portion and a circumferential end of the skirt portion. The bending portion bends in a step-like manner from the outside surface of the pin boss portion toward the circumferential end of the skirt portion.

Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

Abstract: According to one embodiment, a memory system includes a memory chip and a controller. The controller is configured to count a first elapsed time from a start of an Erase process when causing the memory chip to execute the Erase process. The controller is configured to cause the memory chip to interrupt the Erase process after the first elapsed time exceeds a threshold value.

Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Abstract: Disclosed is a composition for improving lipid metabolism. The composition for improving lipid metabolism comprises a cis9,trans11-conjugated linolic acid and a fish oil as active ingredients.

Abstract: To provide a data transmitting apparatus and the like capable of enhancing error detection accuracy without increasing a bandwidth unnecessarily used for the error detection performed on encrypted data and minimizing deterioration in sound quality of the data by effectively reducing noises in the transmission of the data through networks for cars and the like even though the data transmitting apparatus has been simply structured. The present invention makes it possible to perform error detection on audio data according to the sizes of encrypted blocks or packets using simple error check codes embedded in the audio data, or to perform error detection using a variation sequence of attribute information to be transmitted together with the audio data. In this case, output of the sound resulting from the audio data having an error is stopped.

Abstract: A network control circuit that is connected to a controller and a shared memory via busses and to an external apparatus via a network, and stands between the controller and the external apparatus, the network control circuit comprising: a transmission/reception unit operable to transmit/receive data having a prescribed size to/from the external apparatus in each of transmission cycles of the network; a buffer memory operable to store the data; and a read/write unit operable to read data having a size not greater than the prescribed size from the buffer memory/the shared memory, and write the read data into the shared memory/the buffer memory within a prescribed period included in each of the transmission cycles in which the controller does not use the busses, the size of the data to read depending on a storage status of the buffer memory.