Patents by Inventor Takashi Imura

Takashi Imura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070221996
    Abstract: A reference voltage circuit having a high power supply rejection ratio, and can operate at low voltage is provided. The reference voltage circuit includes a bias circuit constructed such that a depletion type transistor (3) is connected in series to a power supply voltage supply terminal of a load circuit, an enhancement type MOS transistor (4) for detecting current through the load circuit to operate as a current source is connected to the load circuit, a depletion type MOS transistor (5) is connected in series to the transistor (4), and a gate terminal of the transistor (5) is connected to a source terminal of the transistor (5), in which the gate terminal of the depletion type transistor (3) is connected to the source terminal of the depletion type transistor (5).
    Type: Application
    Filed: March 16, 2007
    Publication date: September 27, 2007
    Inventor: Takashi Imura
  • Publication number: 20070210852
    Abstract: Provided is a voltage level shift circuit including: a first voltage level shift circuit formed of a P-channel enhancement type transistor (M1) and an N-channel depletion type MOS transistor (M3); and a second voltage level shift circuit formed of a P-channel enhancement type transistor (M2) and an N-channel depletion type MOS transistor (M4). In the voltage lever shift circuit, a cascode circuit using an N-channel depletion type transistor (M5) is serially connected to the first voltage level shift circuit, a cascode circuit using an N-channel depletion type transistor (M6) is serially connected to the second voltage level shift circuit, and a unit for complementarily controlling bias voltages of the respective cascode circuits. As a result, an output signal of the voltage level shift circuit connected to an input of a differential amplifier circuit, for expanding an input voltage range of a signal, is not affected by fluctuations in power supply voltage.
    Type: Application
    Filed: January 26, 2007
    Publication date: September 13, 2007
    Inventor: Takashi Imura
  • Patent number: 7107504
    Abstract: A test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST (Built Out Self Test) and BIST (Built In Self Test). The test apparatus includes an external test unit, the BIST circuit formed in the semiconductor device, and BOST device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the BIST circuit and pattern data for a timing dependency test is stored in the BOST device.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: September 12, 2006
    Assignee: Fujitsu Limited
    Inventors: Masahiro Sato, Junji Akaza, Nobumi Kodama, Hirohisa Mizuno, Takashi Imura, Yasurou Matsuzaki
  • Publication number: 20030002365
    Abstract: A test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST (Built Out Self Test) and BIST (Built In Self Test). The test apparatus includes an external test unit, the BIST circuit formed in the semiconductor device, and BOST device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the BIST circuit and pattern data for a timing dependency test is stored in the BOST device.
    Type: Application
    Filed: February 13, 2002
    Publication date: January 2, 2003
    Applicant: Fujitsu Limited
    Inventors: Masahiro Sato, Junji Akaza, Nobumi Kodama, Hirohisa Mizuno, Takashi Imura, Yasurou Matsuzaki