Patents by Inventor Takashi Ipposhi

Takashi Ipposhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6150696
    Abstract: A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: November 21, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Shigenobu Maeda, Yuichi Hirano
  • Patent number: 6124619
    Abstract: In order to improve isolation between an FS (field shielding) electrode and a gate electrode (6), upper and lower major surfaces of a polysilicon layer (35) forming a principal part of an FS electrode (5) are covered with nitride films (SiN films) (34, 36) respectively. Therefore, it is possible to inhibit portions in the vicinity of edge portions of the polysilicon layer (35) from being oxidized by an oxidant following oxidation for forming a gate insulating film (14). Thus, the polysilicon layer (35) is inhibited from deformation following oxidation, whereby the distance between an FS electrode (5) and a gate electrode (6) is sufficiently ensured. Consequently, isolation between the FS electrode (5) and the gate electrode (6) is improved.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: September 26, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigenobu Maeda, Shigeto Maegawa, Takashi Ipposhi, Yasuo Yamaguchi, Toshiaki Iwamatsu
  • Patent number: 6096583
    Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: August 1, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue
  • Patent number: 6064090
    Abstract: On an insulating film a mesa-isolation silicon layer is formed, in which a channel region and source/drain regions are included. A gate insulating film and a conducting layer as a part of a gate electrode are stacked on the mesa-isolation silicon layer. A sidewall of an insulating material is formed on side surfaces of the mesa-isolation silicon layer, gate insulating film, and conducting layer at an end portion of the channel region of the mesa-isolation silicon layer, and a gate electrode is formed on the conducting layer.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: May 16, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shoichi Miyamoto, Takashi Ipposhi
  • Patent number: 6025629
    Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: February 15, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu, Yasuo Yamaguchi
  • Patent number: 6017781
    Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: January 25, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Satoshi Shimizu, Shuichi Ueno, Shigenobu Maeda, Takashi Ipposhi
  • Patent number: 5933745
    Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between adjacent element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is filled-in or buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: August 3, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 5910672
    Abstract: This invention provides a semiconductor device with a SOI structure and a method of manufacturing the same, preventing deterioration in and making improvement in device characteristics. Nitrogen ion implantation into NMOS and PMOS regions (NR, PR) with resists (22b) and (22c) as masks, respectively, introduces nitrogen ions into channel doped layers (31). The subsequent thermal treatment provides a structure with the channel doped layers (31) containing nitrogen having a prescribed concentration distribution in the depth direction.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: June 8, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 5841171
    Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.
    Type: Grant
    Filed: November 18, 1996
    Date of Patent: November 24, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue
  • Patent number: 5808341
    Abstract: FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: September 15, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigenobu Maeda, Yasuo Yamaguchi, Il Jung Kim, Yasuo Inoue, Shigeto Maegawa, Takashi Ipposhi
  • Patent number: 5736438
    Abstract: In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 7, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hisayuki Nishimura, Kazuyuki Sugahara, Shigenobu Maeda, Takashi Ipposhi, Yasuo Inoue, Toshiaki Iwamatsu, Mikio Ikeda, Tatsuya Kunikiyo, Junji Tateishi, Tadaharu Minato
  • Patent number: 5719426
    Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between the element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: February 17, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 5600154
    Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: February 4, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Satoshi Shimizu, Shuichi Ueno, Shigenobu Maeda, Takashi Ipposhi
  • Patent number: 5528054
    Abstract: Generation of new crystal defects in a monocrystalline semiconductor layer caused by heat treatment, oxidation treatment or polishing treatment is prevented in a method of manufacturing a semiconductor device of an SOI structure. Thus, unevenness in the properties of active devices formed on the monocrystalline semiconductor layers and their malfunctions can be restrained. A non-monocrystalline semiconductor layer formed on an insulator layer is melted to have a prescribed temperature distribution, and monocrystallized. The region of the obtained monocrystalline semiconductor layer corresponding to a high temperature portion in melting is selectively removed before the monocrystalline semiconductor layer is subjected to heat-treatment. Active devices are formed on the resultant island shaped monocrystalline semiconductor layers. The surface of the island shaped monocrystalline semiconductor layer may be polished to be planarized before the formation of the active device.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: June 18, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Ipposhi, Kazuyuki Sugahara
  • Patent number: 5514880
    Abstract: In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.
    Type: Grant
    Filed: October 28, 1993
    Date of Patent: May 7, 1996
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hisayuki Nishimura, Kazuyuki Sugahara, Shigenobu Maeda, Takashi Ipposhi, Yasuo Inoue, Toshiaki Iwamatsu, Mikio Ikeda, Tatsuya Kunikiyo, Junji Tateishi, Tadaharu Minato
  • Patent number: 5504376
    Abstract: In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: April 2, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Sugahara, Natsuo Ajika, Toshiaki Ogawa, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 5471086
    Abstract: Disclosed herein a semiconductor pressure sensor, which is capable of carrying out temperature compensation in high accuracy, having a piezo resistance layer consisting of a single crystal layer formed by lateral seeding. In this semiconductor pressure sensor, a piezo resistance is so formed as to contain no crystal sub-grain boundary. Thus prevented is inconvenience of reduction in resistance temperature coefficient, which is caused when the piezo resistance contains the crystal sub-grain boundary. Thus, the piezo resistance can be set at a high resistance temperature coefficient, whereby a semiconductor pressure sensor capable of carrying out temperature compensation in high accuracy is obtained.
    Type: Grant
    Filed: October 31, 1992
    Date of Patent: November 28, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Ipposhi, Tadashi Nishimura
  • Patent number: 5413968
    Abstract: A semiconductor device includes a conductor layer (3, 7) having a silicon crystal, an insulator layer (5, 15) formed on the surface of the conductor layer (3, 7) having a contact hole therethrough to said surface of the conductor layer (3, 7), an interconnecting portion formed at a predetermined location in the insulator layer (5, 15) and having a contact hole (6, 9) the bottom surface of which becomes the surface of the conductor layer (3, 7), a barrier layer (14) formed at the bottom of said contact hole at least on the surface of the conductor layer (3, 7) in the interconnecting portion, and a metal silicide layer (12) formed on the barrier layer (14).
    Type: Grant
    Filed: February 25, 1993
    Date of Patent: May 9, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Inoue, Kazuyuki Sugahara, Takashi Ipposhi, Yasuo Yamaguchi, Tadashi Nishimura
  • Patent number: 5381235
    Abstract: The present invention provides a three-dimensional shape measuring device and a sensor employed for the three-dimensional shape measuring device.
    Type: Grant
    Filed: December 15, 1992
    Date of Patent: January 10, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Inoue, Tadashi Nishimura, Takashi Ipposhi, Toshiaki Iwamatsu
  • Patent number: 5357365
    Abstract: A laser beam irradiating apparatus is capable of laser annealing with high precision and uniform over the entire surface of a sample. Luminous flux of the laser beam output from a laser source is expanded by a beam expander. The power of the laser beam which has passed through the beam expander is adjusted by a half-wave plate of synthetic quarts and a polarizing prism of synthetic quarts. The laser beam emitted from polarizing prism is guided to a prescribed position by mirrors, and swung in the direction of the X-axis by an X-axis rotation mirror. The laser beam reflected from X-axis rotation mirror has its diameter reduced by a f-.theta. lens to have a prescribed beam spot diameter on the surface of a silicon wafer, and laser beam scanning is carried out at a constant speed.
    Type: Grant
    Filed: May 18, 1993
    Date of Patent: October 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Ipposhi, Tadashi Nishimura