Patents by Inventor Takashi Ipposhi

Takashi Ipposhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040094803
    Abstract: Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).
    Type: Application
    Filed: November 17, 2003
    Publication date: May 20, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
  • Publication number: 20040087118
    Abstract: Activation of impurities is achieved without involving creation of a crystal defect or deformation by using phonon absorption. A laser beam (42) having a wavelength in a range of 16 to 17 &mgr;m is irradiated onto silicon, to cause phonon absorption. Before an energy supplied from the laser beam (42) diffuses around a portion which is irradiated with the laser beam (42), solid phase epitaxy in the portion finishes. Accordingly, crystallization occurs only in the portion which is irradiated with the laser beam (42), and does not occur in a portion which is not irradiated with the laser beam (42). Hence, heat is not excessively absorbed. Also, local phase change such as melting and solidification is not caused.
    Type: Application
    Filed: June 30, 2003
    Publication date: May 6, 2004
    Applicants: Renesas Technology Corp., Ion Engineering Research Institute, Corporation, Natsuro Tsubouchi
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Kazunobu Ohta, Yasuo Inoue, Masanobu Kohara, Takashi Eura, Natsuro Tsubouchi
  • Patent number: 6727572
    Abstract: A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film includes a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: April 27, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu
  • Patent number: 6707105
    Abstract: Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: March 16, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
  • Publication number: 20040046216
    Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.
    Type: Application
    Filed: September 9, 2003
    Publication date: March 11, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Hideki Naruoka, Nobuyoshi Hattori, Shigeto Maegawa, Yasuo Yamaguchi, Takuji Matsumoto
  • Patent number: 6703953
    Abstract: A channel region (2), a source region (3) and a drain region (4) are formed on a polycrystalline semiconductor layer (1). The characteristic of a polycrystalline TFT (101) is dispersed by the amount of crystal grain boundaries (6) contained in the channel region (2). A drain current is reduced as the amount of the crystal grain boundaries (6) contained in the channel region (2) is increased. In order to utilize a code obtained by encoding the electric characteristic of the TFT (101) for identification of a semiconductor chip, a system or the like, the TFT (101) is mounted on the semiconductor chip, the system or the like along with an encoder circuit. Thus, a barrier against illegal use of a user terminal is improved at a low cost.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: March 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Takashi Ipposhi, Hirotada Kuriyama, Hiroki Honda
  • Patent number: 6693324
    Abstract: A semiconductor layer has one end placed on top of a first conductive layer and in contact with the first conductive layer, and the other end placed on top of a second conductive layer and in contact with the second conductive layer. At the central portion, the semiconductor layer faces a gate electrode layer with a gate insulating layer interposed therebetween. The semiconductor layer is formed so that its width W1 is smaller than its height H1. As a result, a thin film transistor and manufacturing method thereof can be obtained in which contact between a source/drain region of the thin film transistor and an upper or lower conductive layer can be made stably.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: February 17, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu
  • Publication number: 20040026762
    Abstract: It is an object to provide a semiconductor device in which a resistance value of a resistor formed by a silicon film is changed with difficulty. A resistor (31) is formed by an amorphous silicon film, and silicides (32a) and (32b) are formed in connecting portions of contact plugs (5a) and (5b) in a surface portion thereof. Since the resistor (31) is the amorphous silicon, a hydrogen atom is bonded with more difficulty as compared with the case in which polycrystalline silicon is used for a material of the resistor. Thus, it is possible to obtain a semiconductor device in which a resistance value of the resistor formed by the silicon film is changed with difficulty. Moreover, the suicides (32a) and (32b) are formed in the connecting portions of the contact plugs (5a) and (5b). Therefore, when contact holes for the contact plugs (5a) and (5b) are to be formed on a first interlayer insulating film (4a) by etching, the resistor (31) is etched with difficulty.
    Type: Application
    Filed: June 12, 2003
    Publication date: February 12, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Yuuichi Hirano, Takuji Matsumoto, Takashi Ipposhi
  • Publication number: 20030218213
    Abstract: By ion implantation process, a P-type impurity for element isolation is implanted at an impurity concentration (P1) into a silicon layer (3) defined between the bottom surface of an element isolation insulating film (5a) and the upper surface of a BOX layer (2). Resulting from this implantation, a P-type impurity is implanted at an impurity concentration (P2) into the silicon layer (3) under a gate oxide film (7a) and in the vicinity of an interface between the silicon layer (3) and the BOX layer (2). Under a capacitor dielectric film (7b) and in the vicinity of an interface between the silicon layer (3) and the BOX layer (2), the silicon layer (3) has an impurity concentration (P0) which is the initial concentration of itself.
    Type: Application
    Filed: November 12, 2002
    Publication date: November 27, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
  • Patent number: 6646306
    Abstract: A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: November 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Hideki Naruoka, Nobuyoshi Hattori, Shigeto Maegawa, Yasuo Yamaguchi, Takuji Matsumoto
  • Publication number: 20030207548
    Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.
    Type: Application
    Filed: April 28, 2003
    Publication date: November 6, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA, Tokyo, Japan
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu, Yasuo Yamaguchi
  • Publication number: 20030201494
    Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
    Type: Application
    Filed: October 2, 2002
    Publication date: October 30, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Shigenobu Maeda, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20030197223
    Abstract: A semiconductor device comprising an SOI substrate fabricated by forming a silicon layer 3 on an insulating layer 2, a plurality of active regions 3 horizontally arranged in the silicon layer 3, and element isolating parts 5 having a trench-like shape which is made of an insulator 5 embedded between the active regions 3 in the silicon layer 3, wherein the insulating layer 2 has spaces 6 positioned in the vicinity of interfaces between the active regions and the element isolating parts 5, whereby it becomes possible to reduce fixed charges or holes existing on a side of the insulating layer in interfaces between the silicon layer and the insulating layer, which fixed charges or holes are generated in a process of oxidation for forming the insulating layer on a bottom surface of the silicon layer.
    Type: Application
    Filed: May 8, 2003
    Publication date: October 23, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Shoichi Miyamoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 6627512
    Abstract: In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: September 30, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Takuji Matsumoto
  • Publication number: 20030160715
    Abstract: A channel region (2), a source region (3) and a drain region (4) are formed on a polycrystalline semiconductor layer (1). The characteristic of a polycrystalline TFT (101) is dispersed by the amount of crystal grain boundaries (6) contained in the channel region (2). A drain current is reduced as the amount of the crystal grain boundaries (6) contained in the channel region (2) is increased. In order to utilize a code obtained by encoding the electric characteristic of the TFT (101) for identification of a semiconductor chip, a system or the like, the TFT (101) is mounted on the semiconductor chip, the system or the like along with an encoder circuit. Thus, a barrier against illegal use of a user terminal is improved at a low cost.
    Type: Application
    Filed: December 10, 1999
    Publication date: August 28, 2003
    Inventors: Shigenobu Maeda, Takashi Ipposhi, Hirotada Kuriyama, Hiroki Honda
  • Patent number: 6611041
    Abstract: A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: August 26, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigenobu Maeda, Yasuo Yamaguchi, Yuuichi Hirano, Takashi Ipposhi, Takuji Matsumoto
  • Patent number: 6603174
    Abstract: An SOI substrate (30) comprises a buried oxide film (2), an SOI layer (3) formed on a first region (51) of the surface (2S) of the buried oxide film, and a silicon oxide film (8) formed on a second region (52) of the surface (2S). Formed on the peripheral portion of the SOI layer (3) is a silicon oxide film (6), the side surface (6H) of which is integrally joined to the side surface (8H) of the silicon oxide film (8). The thickness of the peripheral portion of the SOI layer (3) decreases as closer to the end portion (3H) of the SOI layer (3), while the thickness of the silicon oxide film (6) formed on the peripheral portion of the SOI layer (3) increases as closer to the end portion (3H). A gate oxide film (9) is formed on a predetermined region of the surface of the SOI layer (3), and joined to the silicon oxide film (6) at its end portion.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: August 5, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shoichi Miyamoto, Yuuichi Hirano, Takashi Ipposhi
  • Patent number: 6596615
    Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: July 22, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu, Yasuo Yamaguchi
  • Patent number: 6586802
    Abstract: A semiconductor device comprising an SOI substrate fabricated by forming a silicon layer 3 on an insulating layer 2, a plurality of active regions 3 horizontally arranged in the silicon layer 3, and element isolating parts 5 having a trench-like shape which is made of an insulator 5 embedded between the active regions 3 in the silicon layer 3, wherein the insulating layer 2 has spaces 6 positioned in the vicinity of interfaces between the active regions and the element isolating parts 5, whereby it becomes possible to reduce fixed charges or holes existing on a side of the insulating layer in interfaces between the silicon layer and the insulating layer, which fixed charges or holes are generated in a process of oxidation for forming the insulating layer on a bottom surface of the silicon layer.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: July 1, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shoichi Miyamoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20030119245
    Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask (RM12) is formed so as to have an opening over a region (PR) in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film (PT11) and a peak of an impurity profile is generated in an SOI layer (3), thereby forming a channel stop layer (N1) in the SOI layer (3) under the partial isolation oxide film (PT11), that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer (N1) is set to 1×1017 to 1x1019/cm3.
    Type: Application
    Filed: September 9, 2002
    Publication date: June 26, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Takuji Matsumoto, Shigenobu Maeda