Patents by Inventor Takashi Kitae
Takashi Kitae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9426899Abstract: An electronic component assembly including a first electronic component including a plurality of first electrodes provided on a first major surface of the first electronic component; and a second electronic component including a plurality of second electrodes provided on a first major surface of the second electronic component. A resin including solder powder is provided between the first electronic component and the second electronic component. Also, solder connections are provided to electrically interconnect the first and second electrodes. Elongated grooves are provided in surfaces of the electronic components. The grooves are provided for generation of bubbles during the process for producing the electronic component assembly to promote movement of the solder powder.Type: GrantFiled: April 24, 2008Date of Patent: August 23, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takashi Kitae, Seiichi Nakatani, Seiji Karashima
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Patent number: 8887383Abstract: An electrode structure 100 on which a solder bump is placed includes an electrode pattern 50 made of an electrode-constituting material selected from the group consisting of Cu, Al, Cr, and Ti, a Ni layer 52 formed on a part of the electrode pattern 50, a Pd layer 54 formed on at least a part of a region other than the part of the electrode pattern 50, and an Au layer 56 formed on the Ni layer 52 and the Pd layer 54.Type: GrantFiled: November 27, 2007Date of Patent: November 18, 2014Assignee: Panasonic CorporationInventors: Yasushi Taniguchi, Seiichi Nakatani, Takashi Kitae, Seiji Karashima, Kenichi Hotehama
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Patent number: 8709293Abstract: There is provided a flip-chip mounting resin composition which can be used for a flip-chip mounting process that is high in productivity and reliability and thus can be applicable to a flip-chip mounting of a next-generation LSI. This flip-chip mounting resin composition comprises a resin, metal particles and a convection additive 12 that boils upon heating the resin 13. Upon the heating of the resin 13, the metal particles melt and the boiling convection additive 12 convects within the resin 13. This flip-chip mounting resin composition is supplied between a circuit substrate 10 and a semiconductor chip 20, and subsequently the resin 13 is heated so that the molten metal particles self-assemble into the region between each electrode of the circuit substrate and each electrode of the semiconductor chip. As a result, an electrical connection is formed between each electrode of the circuit substrate and each electrode of the semiconductor chip.Type: GrantFiled: December 14, 2005Date of Patent: April 29, 2014Assignee: Panasonic CorporationInventors: Takashi Kitae, Seiji Karashima, Koichi Hirano, Toshiyuki Kojima, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita
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Patent number: 8501583Abstract: A resin containing a conductive particle and a gas bubble generating agent is supplied in a space between the substrates each having a plurality of electrodes. The resin is then heated to melt the conductive particle contained in the resin and generate gas bubbles from the gas bubble generating agent. A step portion is formed on at least one of the substrates. In the process of heating the resin, the resin is pushed aside by the growing gas bubbles, and as a result of that, the conductive particle contained in the resin is led to a space between the electrodes, and a connector is formed in the space. At the same time, the resin is led to a space between parts of the substrates at which the step portion is formed, and cured to fix the distance between the substrates.Type: GrantFiled: July 6, 2009Date of Patent: August 6, 2013Assignee: Panasonic CorporationInventors: Takashi Kitae, Seiji Karashima, Susumu Sawada, Seiichi Nakatani
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Patent number: 8297488Abstract: A method for forming bumps 19 on electrodes 32 of a wiring board 31 includes the steps of: (a) supplying a fluid 14 containing conductive particles 16 and a gas bubble generating agent onto a first region 17 including the electrodes 32 on the wiring board 31; (b) disposing a substrate 40 having a wall surface 45 formed near the electrodes 32 for forming a meniscus 55 of the fluid 14, so that the substrate 40 faces the wiring board 31; and (c) heating the fluid 14 to generate gas bubbles 30 from the gas bubble generating agent contained in the fluid 14.Type: GrantFiled: February 22, 2007Date of Patent: October 30, 2012Assignee: Panasonic CorporationInventors: Seiji Karashima, Yasushi Taniguchi, Seiichi Nakatani, Kenichi Hotehama, Takashi Kitae, Susumu Sawada
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Patent number: 8288778Abstract: A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided. A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, an organic semiconductor disposed inside the through hole, an insulating film on one end of the organic semiconductor, a gate electrode on the insulating film, a source electrode connected electrically to the other end of the organic semiconductor and a drain electrode connected electrically to the other end of the organic semiconductor.Type: GrantFiled: August 6, 2008Date of Patent: October 16, 2012Assignee: Panasonic CorporationInventors: Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Susumu Sawada
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Patent number: 8283246Abstract: The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing each other; ejecting a gas (9a) from a gas generation source (1) included in the first electronic component (2) by heating the first electronic component (2) and the solder resin composition; and inducing the flow of the solder powder (5a) in the solder resin composition (6) by inducing convection of the gas (9a) in the solder resin composition (6), and electrically connecting the connecting terminals (3) and the electrode terminals (7) by self-assembly on the connecting terminals (3) and the electrode terminals (7).Type: GrantFiled: April 21, 2011Date of Patent: October 9, 2012Assignee: Panasonic CorporationInventors: Takashi Kitae, Seiichi Nakatani, Seiji Karashima, Yoshihisa Yamashita, Takashi Ichiryu
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Patent number: 8193526Abstract: A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided. A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, a source electrode disposed along the inner wall of the through hole, a drain electrode disposed along the inner wall of the through hole, a gate electrode disposed on the other surface of the resin film opposing the through hole, an insulating layer disposed on the gate electrode at the bottom of the through hole and an organic semiconductor disposed in the through hole so as to contact the source electrode and the drain electrode, wherein the organic semiconductor makes contact with at least a part of the insulating layer at the bottom of the through hole so that a channel is formed in the organic semiconductor in the vicinity of the insulating layer that is in contact therewith.Type: GrantFiled: August 6, 2008Date of Patent: June 5, 2012Assignee: Panasonic CorporationInventors: Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Susumu Sawada
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Patent number: 8097958Abstract: A connection structure (package 10) has a first plate body 101 and a second plate body; in the first plate body 101, a wiring pattern having a plurality of connection terminals 102 is formed, and the second plate body has at least two connection terminals (electrode terminals 104) arranged facing the connection terminals of the first plate body 101. The connection terminals of the first and second plate bodies are connection terminals formed as projections on the surfaces of the first and second plate bodies. A conductive substance 108 is accumulated to cover at least a part of each side face of the connection terminals opposed to each other of the first and second plate bodies, and the connection terminals thus opposed are connected to each other via the conductive substance. The package thus formed is ready for a high-pin-count, narrow-pitch configuration of a next-generation semiconductor chip, and exhibits excellent productivity and reliability.Type: GrantFiled: April 18, 2007Date of Patent: January 17, 2012Assignee: Panasonic CorporationInventors: Susumu Sawada, Seiichi Nakatani, Seiji Karashima, Takashi Kitae
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Patent number: 8071425Abstract: The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217).Type: GrantFiled: April 21, 2010Date of Patent: December 6, 2011Assignee: Panasonic CorporationInventors: Seiichi Nakatani, Takashi Kitae, Yoshihisa Yamashita, Takashi Ichiryu, Seiji Karashima
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Patent number: 8039307Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.Type: GrantFiled: March 22, 2010Date of Patent: October 18, 2011Assignee: Panasonic CorporationInventors: Toshiyuki Kojima, Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Shingo Komatsu
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Patent number: 8012801Abstract: A flip chip mounting process includes the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (II), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. The heating step is carried out at a temperature that is higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12). During this heating step, the melted solder powder is allowed to self-assemble into the region between each electrode terminal (11) of the wiring substrate (10) and each connecting terminal (21) of the semiconductor chip to form an electrical connection between each electrode terminal (11) and each connecting terminal (21).Type: GrantFiled: March 4, 2010Date of Patent: September 6, 2011Assignee: Panasonic CorporationInventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
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Publication number: 20110204366Abstract: A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided. A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, an organic semiconductor disposed inside the through hole, an insulating film on one end of the organic semiconductor, a gate electrode on the insulating film, a source electrode connected electrically to the other end of the organic semiconductor and a drain electrode connected electrically to the other end of the organic semiconductor.Type: ApplicationFiled: August 6, 2008Publication date: August 25, 2011Applicant: PANASONIC CORPORATIONInventors: Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Susumu Sawada
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Publication number: 20110204367Abstract: A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided. A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, a source electrode disposed along the inner wall of the through hole, a drain electrode disposed along the inner wall of the through hole, a gate electrode disposed on the other surface of the resin film opposing the through hole, an insulating layer disposed on the gate electrode at the bottom of the through hole and an organic semiconductor disposed in the through hole so as to contact the source electrode and the drain electrode, wherein the organic semiconductor makes contact with at least a part of the insulating layer at the bottom of the through hole so that a channel is formed in the organic semiconductor in the vicinity of the insulating layer that is in contact therewith.Type: ApplicationFiled: August 6, 2008Publication date: August 25, 2011Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Susumu Sawada
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Publication number: 20110201195Abstract: The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing each other; ejecting a gas (9a) from a gas generation source (1) included in the first electronic component (2) by heating the first electronic component (2) and the solder resin composition; and inducing the flow of the solder powder (5a) in the solder resin composition (6) by inducing convection of the gas (9a) in the solder resin composition (6), and electrically connecting the connecting terminals (3) and the electrode terminals (7) by self-assembly on the connecting terminals (3) and the electrode terminals (7).Type: ApplicationFiled: April 21, 2011Publication date: August 18, 2011Applicant: PANASONIC CORPORATIONInventors: Takashi KITAE, Seiichi NAKATANI, Seiji KARASHIMA, Yoshihisa YAMASHITA, Takashi ICHIRYU
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Patent number: 7951700Abstract: The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing each other; ejecting a gas (9a) from a gas generation source (1) included in the first electronic component (2) by heating the first electronic component (2) and the solder resin composition; and inducing the flow of the solder powder (5a) in the solder resin composition (6) by inducing convection of the gas (9a) in the solder resin composition (6), and electrically connecting the connecting terminals (3) and the electrode terminals (7) by self-assembly on the connecting terminals (3) and the electrode terminals (7).Type: GrantFiled: March 16, 2006Date of Patent: May 31, 2011Assignee: Panasonic CorporationInventors: Takashi Kitae, Seiichi Nakatani, Seiji Karashima, Yoshihisa Yamashita, Takashi Ichiryu
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Patent number: 7921551Abstract: An electronic component mounting method includes a step of applying a resin composition (3) including solder powder, convective additive and resin having fluidity at the melting temperature of the solder powder on a main surface of a wiring substrate (1) provided with conductive wirings and connecting terminals, a step of preparing a group of electronic components consisting of a plurality of electronic components (7, 8 and 9) including at least a passive component, the respective electronic components comprising electrode terminals, position-aligning connecting terminals with the electrode terminals, and making the group of electronic components abut a surface of the resin composition, a step of heating at least the resin composition so as to melt solder powder and make the solder powder self-assembled between the connecting terminals and the electrode terminals by the convective additive, and thereby connecting the connecting terminals and the electrode terminals by soldering, and a step of fixedly adheringType: GrantFiled: March 23, 2006Date of Patent: April 12, 2011Assignee: Panasonic CorporationInventors: Yoshihisa Yamashita, Seiji Karashima, Takashi Kitae, Seiichi Nakatani, Toshiyuki Kojima, Shingo Komatsu
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Patent number: 7919357Abstract: A resin containing conductive particles and a gas bubble generating agent is supplied between a first substrate and a second substrate, and then the resin is heated to generate gas bubbles from the gas bubble generating agent contained in the resin so that the resin is self-assembled between electrodes. Then, the resin is further heated to melt the conductive particles contained in the resin, thereby forming connectors between electrodes. A partition member sealing the gap between the substrates is provided near a peripheral portion of the resin, and gas bubbles in the resin are discharged to the outside through the peripheral portion of the resin where the partition member is absent.Type: GrantFiled: June 23, 2009Date of Patent: April 5, 2011Assignee: Panasonic CorporationInventors: Susumu Sawada, Seiichi Nakatani, Seiji Karashima, Takashi Kitae
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Patent number: 7911064Abstract: A mounted body of the present invention includes: a multilayer semiconductor chip 20 including a plurality of semiconductor chips 10 (10a, 10b) that are stacked; and a mounting board 13 on which the multilayer semiconductor chip 20 is mounted. In this mounted body, each of the semiconductor chips 10 (10a, 10b) in the multilayer semiconductor chip 20 has a plurality of element electrodes 12 (12a, 12b) on a chip surface 21 (21a, 21b) facing toward the mounting board 13. On the mounting board 13, electrode terminals 14 are formed so as to correspond to the plurality of element electrodes (12a, 12b), respectively, and the electrode terminals 14 of the mounting board and the element electrodes (12a, 12b) are connected electrically to each other via solder bump formed as a result of assembly of solder particles. With this configuration, a mounted body on which a stacked package is mounted can be manufactured easily.Type: GrantFiled: February 28, 2006Date of Patent: March 22, 2011Assignee: Panasonic CorporationInventors: Shingo Komatsu, Seiichi Nakatani, Seiji Karashima, Toshiyuki Kojima, Takashi Kitae, Yoshihisa Yamashita
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Patent number: 7905011Abstract: In a method for forming bumps 19 on electrodes 32 of a wiring board 31, a fluid 14 containing conductive particles 16 and a gas bubble generating agent is supplied onto a first region 17 including the electrodes 32 on the wiring board 31. Then, a substrate 40 which has a protruding surface 13 having the same area as that of the first region 17 and formed on a main surface 18 of the substrate 40 having a larger area than that of the first region 17 is disposed so that the protruding surface 13 faces the first region 17 of the wiring board 31. Then, the fluid 14 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the fluid 14.Type: GrantFiled: February 22, 2007Date of Patent: March 15, 2011Assignee: Panasonic CorporationInventors: Yasushi Taniguchi, Seiichi Nakatani, Seiji Karashima, Takashi Kitae, Susumu Matsuoka, Masayoshi Koyama