Patents by Inventor Takashi Kitahara

Takashi Kitahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9825156
    Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: November 21, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara
  • Publication number: 20170317002
    Abstract: A power amplifier module includes a substrate, a power amplifier having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces a principal surface of the substrate, a surface acoustic wave duplexer having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces the principal surface of the substrate, a heat dissipation unit defined on another principal surface of the substrate, a heat dissipation path that connects a connecting portion between the power amplifier and the principal surface to the heat dissipation unit, an insulating resin that covers the power amplifier and the surface acoustic wave duplexer, a conductive shield that covers the insulating resin, and a first conductive unit defined on the second surface of the surface acoustic wave duplexer and electrically connected to the conductive shield.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 2, 2017
    Inventors: Takashi Kitahara, Hiroaki Nakayama, Tsunekazu Saimei, Hiroki Noto, Koichiro Kawasaki
  • Publication number: 20170273183
    Abstract: An electronic component includes an electronic component element including first and second main surfaces, a heat-dissipation accelerating member on the first main surface, a sealing resin layer sealing the electronic component element, and a shielding member provided on the sealing resin layer and electrically connected to the heat-dissipation accelerating member. The heat-dissipation accelerating member includes fourth and fifth main surfaces. The electronic component includes a connecting member disposed on the fifth main surface of the heat-dissipation accelerating member and electrically connecting at least one portion of the heat-dissipation accelerating member and the shielding member. The connecting member has a higher thermal conductivity than the sealing resin layer. The contact area between the heat-dissipation accelerating member and the connecting member is smaller than the area of the fifth main surface.
    Type: Application
    Filed: June 1, 2017
    Publication date: September 21, 2017
    Inventors: Koichiro KAWASAKI, Taku KIKUCHI, Takashi KITAHARA, Hiroki NOTO
  • Patent number: 9768639
    Abstract: The vehicle-mounted power source device comprising: a low-voltage battery; a high-voltage battery; a boost unit that boosts electrical power for charging the high-voltage battery; a solar panel that converts solar light to electrical power; a bi-directional buck-boost unit that boosts/bucks the electrical power converted by the solar panel; and a control unit that performs control in a manner so as to charge the low-voltage battery by means of electrical power of which the voltage has been altered by the buck-boost unit. When the amount of stored electrical power at the low-voltage battery is at least a predetermined value, the control unit performs control in a manner so that the electrical power stored at the low-voltage battery is boosted by the boost unit and the bi-directional buck-boost unit, and the high-voltage battery is charged by means of the boosted electrical power.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: September 19, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takashi Nakazawa, Takashi Kitahara
  • Publication number: 20160343837
    Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.
    Type: Application
    Filed: August 5, 2016
    Publication date: November 24, 2016
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA
  • Publication number: 20160155830
    Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.
    Type: Application
    Filed: November 4, 2015
    Publication date: June 2, 2016
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA
  • Patent number: 9317438
    Abstract: A cache memory apparatus according to the present invention includes a cache memory that caches an instruction code corresponding to a fetch address and a cache control circuit that controls the instruction code to be cached in the cache memory. The cache control circuit caches an instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine and disables the instruction code to be cached when the number of the instruction codes to be cached exceeds a previously set maximum number.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: April 19, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Kitahara
  • Publication number: 20150280487
    Abstract: The vehicle-mounted power source device comprising: a low-voltage battery; a high-voltage battery; a boost unit that boosts electrical power for charging the high-voltage battery; a solar panel that converts solar light to electrical power; a bi-directional buck-boost unit that boosts/bucks the electrical power converted by the solar panel; and a control unit that performs control in a manner so as to charge the low-voltage battery by means of electrical power of which the voltage has been altered by the buck-boost unit. When the amount of stored electrical power at the low-voltage battery is at least a predetermined value, the control unit performs control in a manner so that the electrical power stored at the low-voltage battery is boosted by the boost unit and the bi-directional buck-boost unit, and the high-voltage battery is charged by means of the boosted electrical power.
    Type: Application
    Filed: October 22, 2013
    Publication date: October 1, 2015
    Inventors: Takashi Nakazawa, Takashi Kitahara
  • Publication number: 20150252882
    Abstract: A stepless transmission 100 includes: a primary damper 30 placed between an engine output shaft 21 and an input shaft 11 of a stepless transmission mechanism 10, and elastically connecting the engine output shaft 21 and the input shaft 11; a secondary damper 40 composed of a hub member 41 fixed to the input shaft 11 and a plurality of mass bodies 42 swingably attached to the hub member 41; and a start device 80 provided between external teeth 13a for output and a drive shaft 91.
    Type: Application
    Filed: November 18, 2013
    Publication date: September 10, 2015
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Kazuhiko Yamamoto, Takashi Kitahara, Masaki Sagawa
  • Publication number: 20150214076
    Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.
    Type: Application
    Filed: April 9, 2015
    Publication date: July 30, 2015
    Inventors: Takashi KITAHARA, Hiroshi KOGUMA
  • Patent number: 9030032
    Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kitahara, Hiroshi Koguma
  • Patent number: 9028797
    Abstract: The invention provides an antigen or drug delivery complex containing a complex of an antigen or drug and a cationic molecule, and an anionic molecule encapsulating the same. The antigen or drug delivery complex can be used as a main component of a drug delivery system that delivers various antigens and drugs to a particular cell or organ.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: May 12, 2015
    Assignees: Nagasaki University, Kyusyu University Corporation, National University Corporation Hamamatsu University School of Medicine
    Inventors: Hitoshi Sasaki, Tomoaki Kurosaki, Takashi Kitahara, Hideto To, Katsuyuki Yui, Kenji Hirayama, Kouichi Morita, Takahiro Mukai, Yasuhiro Magata, Mikako Ogawa, Kohei Sano
  • Patent number: 8546939
    Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 1, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Tomonori Tanoue, Sakae Kikuchi, Toshifumi Makino, Takeshi Sato, Tsutomu Kobori, Yasunari Umemoto, Takashi Kitahara
  • Publication number: 20130052127
    Abstract: The invention provides an antigen or drug delivery complex containing a complex of an antigen or drug and a cationic molecule, and an anionic molecule encapsulating the same. The antigen or drug delivery complex can be used as a main component of a drug delivery system that delivers various antigens and drugs to a particular cell or organ.
    Type: Application
    Filed: February 24, 2011
    Publication date: February 28, 2013
    Applicants: NAGASAKI UNIVERSITY, National University Corporation Hamamatsu University School of Medicine, KYUSYU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION
    Inventors: Hitoshi Sasaki, Tomoaki Kurosaki, Takashi Kitahara, Hideto To, Katsuyuki Yui, Kenji Hirayama, Kouichi Morita, Takahiro Mukai, Yasuhiro Magata, Mikako Ogawa, Kohei Sano
  • Publication number: 20120295668
    Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 22, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi KITAHARA, Hiroshi KOGUMA
  • Publication number: 20110026572
    Abstract: A baud rate error detection circuit has an edge detector, a start bit sampling circuit and an abnormal waveform detection circuit. The edge detector receives sync-field used for adjusting a baud rate of serial communication, and generates an edge detection signal in response to an edge included in the sync-field. The start bit sampling circuit measures a bit width of a start bit of the sync-field based on the edge detection signal and an internal clock signal, and generates an expected value signal indicating the bit width of the start bit as an expected value. The abnormal waveform detection circuit measures an inter-edge width after the start bit based on the edge detection signal and the internal clock signal, and generates an abnormal waveform detection signal if an error between the inter-edge width and the expected value indicated by the expected value signal exceeds a predetermined allowable error range.
    Type: Application
    Filed: June 24, 2010
    Publication date: February 3, 2011
    Inventor: Takashi Kitahara
  • Patent number: 7778350
    Abstract: Provided is a multi-carrier communication device capable of reducing the deterioration of a reception quality while suppressing the peak power of a multi-carrier signal. In this device, a clipping strain measurement unit (108) calculates the individual average powers (or the clipping strain powers) of peak suppression signals contained in a center area and in end areas. Moreover, the clipping strain measurement unit (108) uses the calculated clipping strain, to calculates the ratios of the signal powers to the clipping strain powers (or the ratios of the signals to the clipping strains) individually for the center area and the end areas, and outputs the calculated ratios of the signals to the clipping strains to a puncture-modulation mode selection unit (109).
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: August 17, 2010
    Assignee: Panasonic Corporation
    Inventors: Sadaki Futagi, Takashi Kitahara
  • Publication number: 20090180574
    Abstract: Provided is a multi-carrier communication device capable of reducing the deterioration of a reception quality while suppressing the peak power of a multi-carrier signal. In this device, a clipping strain measurement unit (108) calculates the individual average powers (or the clipping strain powers) of peak suppression signals contained in a center area and in end areas. Moreover, the clipping strain measurement unit (108) uses the calculated clipping strain, to calculates the ratios of the signal powers to the clipping strain powers (or the ratios of the signals to the clipping strains) individually for the center area and the end areas, and outputs the calculated ratios of the signals to the clipping strains to a puncture-modulation mode selection unit (109).
    Type: Application
    Filed: September 28, 2005
    Publication date: July 16, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Sadaki Futagi, Takashi Kitahara
  • Patent number: 7522026
    Abstract: New and useful alignment method and system for electromagnets used in the high energy accelerator that can make the installation simple and less time consuming are disclosed. By measuring the multiple of measurement reference points for obtaining the position and posture information of the electromagnet on the high energy accelerator, the deviation of the present value from the installation target value for the electromagnet within the reference coordinates in the building. For each of the adjustment mechanisms such as the multiple of adjustment bolts or the actuators, the Jacobian matrix representing the relationship between the unit operation amount and the posture changes of the electromagnet is obtained.
    Type: Grant
    Filed: November 24, 2006
    Date of Patent: April 21, 2009
    Assignee: Hitachi Plant Technologies, Ltd.
    Inventors: Takashi Kitahara, Shizuo Imaoka, Yuuichi Yamamoto
  • Patent number: 7504116
    Abstract: The present invention relates to a hair growth inhibitor and a depilation accelerator, each comprising a crude drug selected from Bupleuri Radix, Perillae Herba, Rhei Rhizoma and Akebiae Caulis, or an extract thereof. This inhibitor or accelerator makes it possible to inhibit the growth of body hair or promote depilation, respectively, thereby reducing the frequency of hair removal treatment. Moreover, it makes the hair body finer, thereby facilitating the removal of the hair from feet or arms.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: March 17, 2009
    Assignee: Kao Corporation
    Inventors: Etsuji Wakisaka, Takashi Kitahara, Naoko Tsuji, Hiroshi Kusuoku